公开(公告)号：US11113204B2

公开(公告)日：2021-09-07

申请号：US16388478

申请日：2019-04-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bartholomew Blaner ,  Michael S. Siegel ,  Jeffrey A. Stuecheli ,  William J. Starke ,  Kenneth M. Valk ,  John D. Irish ,  Lakshminarayana Arimilli

IPC: G06F12/00 ,  G06F12/10 ,  G06F13/16 ,  G06F9/38 ,  G06F12/0817 ,  G06F12/1027 ,  G06F12/1045 ,  G06F3/06 ,  G06F13/28 ,  G06F9/455

Abstract: An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an accelerator functional unit and an effective address-based accelerator cache for buffering copies of data from the system memory of the coherent data processing system, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit includes request logic that, responsive to receipt on the first communication interface of a translation entry invalidation request, issues to the accelerator unit via the second communication interface an invalidation request that identifies an entry in the effective address-based accelerator cache to be invalidated utilizing a host tag identifying a storage location in the real address-based directory.

公开(公告)号：US11030110B2

公开(公告)日：2021-06-08

申请号：US16395942

申请日：2019-04-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael S. Siegel ,  Bartholomew Blaner ,  Jeffrey A. Stuecheli ,  William J. Starke ,  Derek E. Williams ,  Kenneth M. Valk ,  John D. Irish ,  Lakshminarayana Arimilli

IPC: G06F12/10 ,  G06F13/16 ,  G06F9/38 ,  G06F12/0817 ,  G06F12/1027 ,  G06F12/1045 ,  G06F3/06 ,  G06F13/28 ,  G06F9/455

Abstract: An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes request logic that communicates memory access requests and request responses with the accelerator unit. The request logic, responsive to receipt from the accelerator unit of a read-type request specifying an aliased second effective address of a target cache line, provides a request response including a host tag indicating that the accelerator unit has associated a different first effective address with the target cache line.

公开(公告)号：US11341060B2

公开(公告)日：2022-05-24

申请号：US16990594

申请日：2020-08-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael S. Siegel ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Lakshminarayana Arimilli ,  Kenneth M. Valk ,  James Mikos ,  David Krolak

IPC: G06F12/1009 ,  G06F12/084 ,  G06F13/16 ,  G06F12/06

Abstract: In a data processing environment, a communication interface of a second host data processing system receives, from a first host data processing system, a host command in a first command set. The host command specifies a memory access to a memory coupled to the second host data processing system. The communication interface translates the host command into a command in a different second command set emulating coupling of an attached functional unit to the communication interface. The communication interface presents the second command to a host bus protocol interface of the second host data processing system. Based on receipt of the second command, the host bus protocol interface initiates, on a system fabric of the second host data processing system, a host bus protocol memory access request specifying the memory access.

公开(公告)号：US10761995B2

公开(公告)日：2020-09-01

申请号：US16395976

申请日：2019-04-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bartholomew Blaner ,  Jeffrey A. Stuecheli ,  Michael S. Siegel ,  William J. Starke ,  Curtis C. Wollbrink ,  Kenneth M. Valk ,  Lakshminarayana Arimilli ,  John D. Irish

IPC: G06F12/10 ,  G06F13/16 ,  G06F9/38 ,  G06F12/0817 ,  G06F12/1027 ,  G06F12/1045 ,  G06F3/06 ,  G06F13/28 ,  G06F9/455

Abstract: An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes directory control logic that configures at least a number of congruence classes utilized in the real address-based directory based on configuration parameters specified on behalf of or by the accelerator unit.