公开(公告)号：US12050798B2

公开(公告)日：2024-07-30

申请号：US17388993

申请日：2021-07-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Derek E. Williams ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC: G06F3/06 ,  G06F12/1009 ,  G06F13/28 ,  G06F9/455

CPC classification number: G06F3/0647 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0665 ,  G06F3/067 ,  G06F12/1009 ,  G06F13/28 ,  G06F2009/4557 ,  G06F2009/45583 ,  G06F2212/657

Abstract: A destination host includes a processor core, a system fabric, a memory system, and a link controller communicatively coupled to the system fabric and configured to be communicatively coupled, via a communication link, to a source host with which the destination host is non-coherent. The destination host migrates, via the communication link, a state of a logical partition from the source host to the destination host and page table entries for translating addresses of a dataset of the logical partition from the source host to the destination host. After migrating the state and page table entries, the destination host initiates execution of the logical partition on the processor core while at least a portion of the dataset of the logical partition resides in the memory system of the source host and migrates, via the communication link, the dataset of the logical partition to the memory system of the destination host.

公开(公告)号：US20230036054A1

公开(公告)日：2023-02-02

申请号：US17388993

申请日：2021-07-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： DEREK E. WILLIAMS ,  GUY L. GUTHRIE ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC: G06F3/06 ,  G06F12/1009 ,  G06F13/28

Abstract: A destination host includes a processor core, a system fabric, a memory system, and a link controller communicatively coupled to the system fabric and configured to be communicatively coupled, via a communication link, to a source host with which the destination host is non-coherent. The destination host migrates, via the communication link, a state of a logical partition from the source host to the destination host and page table entries for translating addresses of a dataset of the logical partition from the source host to the destination host. After migrating the state and page table entries, the destination host initiates execution of the logical partition on the processor core while at least a portion of the dataset of the logical partition resides in the memory system of the source host and migrates, via the communication link, the dataset of the logical partition to the memory system of the destination host.

公开(公告)号：US11281582B2

公开(公告)日：2022-03-22

申请号：US16742380

申请日：2020-01-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Derek E. Williams ,  Guy L. Guthrie ,  William J. Starke ,  Hugh Shen

IPC: G06F12/0815

Abstract: A data processing system includes multiple processing units all having access to a shared memory system. A processing unit includes a lower level cache configured to serve as a point of systemwide coherency and a processor core coupled to the lower level cache. The processor core includes an upper level cache, an execution unit that executes a store-conditional instruction to generate a store-conditional request that specifies a store target address and store data, and a flag that, when set, indicates the store-conditional request can be completed early in the processor core. The processor core also includes completion logic configured to commit an update of the shared memory system with the store data specified by the store-conditional request based on whether the flag is set.

公开(公告)号：US11157411B2

公开(公告)日：2021-10-26

申请号：US16691776

申请日：2019-11-22

Applicant: International Business Machines Corporation

Inventor： Sanjeev Ghai ,  Guy L. Guthrie ,  Stephen J. Powell ,  William J. Starke

IPC: G06F12/08 ,  G06F12/0855 ,  G06F12/126

Abstract: An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption.

公开(公告)号：US11113204B2

公开(公告)日：2021-09-07

申请号：US16388478

申请日：2019-04-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bartholomew Blaner ,  Michael S. Siegel ,  Jeffrey A. Stuecheli ,  William J. Starke ,  Kenneth M. Valk ,  John D. Irish ,  Lakshminarayana Arimilli

IPC: G06F12/00 ,  G06F12/10 ,  G06F13/16 ,  G06F9/38 ,  G06F12/0817 ,  G06F12/1027 ,  G06F12/1045 ,  G06F3/06 ,  G06F13/28 ,  G06F9/455

Abstract: An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an accelerator functional unit and an effective address-based accelerator cache for buffering copies of data from the system memory of the coherent data processing system, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit includes request logic that, responsive to receipt on the first communication interface of a translation entry invalidation request, issues to the accelerator unit via the second communication interface an invalidation request that identifies an entry in the effective address-based accelerator cache to be invalidated utilizing a host tag identifying a storage location in the real address-based directory.

公开(公告)号：US11042325B2

公开(公告)日：2021-06-22

申请号：US16532041

申请日：2019-08-05

Applicant: International Business Machines Corporation

Inventor： Jie Zheng ,  Steven R. Carlough ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Stephen J. Powell

IPC: G06F3/06 ,  G06F9/38 ,  G06F9/52

Abstract: A system and associated processes may perform a memory access operation that includes receiving a data packet comprising a command of a type of a plurality of types of commands. The processes may include initiating a decoding of a first portion of the command, and automatically speculating as to the type of the command. Based on the speculation as to the type of the command, a bank activate command may be generated before the data packet is entirely decoded or received.

公开(公告)号：US10991635B2

公开(公告)日：2021-04-27

申请号：US16517568

申请日：2019-07-20

Applicant: International Business Machines Corporation

Inventor： Dale Curtis McHerron ,  Kamal K. Sikka ,  Joshua M. Rubin ,  Ravi K. Bonam ,  Ramachandra Divakaruni ,  William J. Starke ,  Maryse Cournoyer

IPC: H01L23/538 ,  H01L23/13 ,  H01L27/24 ,  H01L23/532

Abstract: The present invention includes a bridge connector with one or more semiconductor layers in a bridge connector shape. The shape has one or more edges, one or more bridge connector contacts on a surface of the shape, and one or more bridge connectors. The bridge connectors run through one or more of the semiconductor layers and connect two or more of the bridge connector contacts. The bridge connector contacts are with a tolerance distance from one of the edges. In some embodiments the bridge connector is a central bridge connector that connects two or more chips disposed on the substrate of a multi-chip module (MCM). The chips have chip contacts that are on an interior corner of the chip. The interior corners face one another. The central bridge connector overlaps the interior corners so that each of one or more of the bridge contacts is in electrical contact with each of one or more of the chip contacts. In some embodiments, overlap is minimized to permit more access to the surface of the chips. Arrays of MCMs and methods of making bridge connects are disclosed. Bridge connector shapes include: rectangular, window pane, plus-shaped, circular shaped, and polygonal-shaped.

公开(公告)号：US20190392143A1

公开(公告)日：2019-12-26

申请号：US16539537

申请日：2019-08-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： William E. Hall ,  Guerney D.H. Hunt ,  Ronald N. Kalla ,  Jentje Leenstra ,  Paul MACKERRAS ,  William J. Starke ,  Jeffrey A. Stuecheli

IPC: G06F21/55 ,  G06F13/364 ,  G06F13/40 ,  G06F12/14 ,  G06F21/53 ,  G06F9/455

Abstract: Secure memory implementation for secure execution of virtual machines. Data is processed in a first mode and a second mode, and commands are sent to a chip interconnect bus using real addresses, wherein the chip interconnect bus includes a number of bits for the real addresses. A memory controller is operatively coupled to a memory component. A secure memory range is specified by using range registers. If the real address is detected to be in the secure memory range to match a memory component address, a real address bit is inverted. If the real address is in the secure memory address hole, a security access violation is detected. If the real address is not in the secure address range and the real address bit is set, the security access violation is detected.

公开(公告)号：US10102130B2

公开(公告)日：2018-10-16

申请号：US15095642

申请日：2016-04-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Guy L. Guthrie ,  Jonathan R. Jackson ,  Michael S. Siegel ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/0815 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0831 ,  G06F12/0893

Abstract: A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and a system interconnect coupled to the system memory and the multiple vertical cache hierarchies. A first cache memory in a first vertical cache hierarchy issues on the system interconnect a request for a target cache line. Responsive to the request and prior to receiving a systemwide coherence response for the request, the first cache memory receives from a second cache memory in a second vertical cache hierarchy by cache-to-cache intervention the target cache line and an early indication of the systemwide coherence response for the request. In response to the early indication of the systemwide coherence response and prior to receiving the systemwide coherence response, the first cache memory initiates processing to install the target cache line in the first cache memory.

公开(公告)号：US09996298B2

公开(公告)日：2018-06-12

申请号：US15243581

申请日：2016-08-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lakshminarayana B. Arimilli ,  Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

IPC: G06F3/06 ,  G06F9/30 ,  G06F12/0897 ,  G06F12/10

CPC classification number: G06F3/065 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/52 ,  G06F12/0292 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/1041 ,  G06F2212/206

Abstract: A processor core of a data processing system, in response to a first instruction, generates a copy-type request specifying a source real address and transmits it to a lower level cache. In response to a second instruction, the processor core generates a paste-type request specifying a destination real address associated with a memory-mapped device and transmits it to the lower level cache. In response to receipt of the copy-type request, the lower level cache copies a data granule from a storage location specified by the source real address into a non-architected buffer. In response to receipt of the paste-type request, the lower level cache issues a command to write the data granule from the non-architected buffer to the memory-mapped device. In response to receipt from the memory-mapped device of a busy response, the processor core abandons the memory move instruction sequence and performs alternative processing.