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公开(公告)号：US20210216457A1
公开(公告)日：2021-07-15
申请号：US16742380
申请日：2020-01-14
IPC分类号： G06F12/0815
摘要： A data processing system includes multiple processing units all having access to a shared memory system. A processing unit includes a lower level cache configured to serve as a point of systemwide coherency and a processor core coupled to the lower level cache. The processor core includes an upper level cache, an execution unit that executes a store-conditional instruction to generate a store-conditional request that specifies a store target address and store data, and a flag that, when set, indicates the store-conditional request can be completed early in the processor core. The processor core also includes completion logic configured to commit an update of the shared memory system with the store data specified by the store-conditional request based on whether the flag is set.
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公开(公告)号：US20180150396A1
公开(公告)日：2018-05-31
申请号：US15364458
申请日：2016-11-30
发明人： ETAI ADAR , LAKSHMINARAYANA B. ARIMILLI , YIFTACH BENJAMINI , BARTHOLOMEW BLANER , WILLIAM J. STARKE , JEFFREY A. STUECHELI
IPC分类号： G06F12/0815 , G06F12/1081 , G06F12/14
CPC分类号： G06F12/0815 , G06F12/1081 , G06F12/145 , G06F13/1668 , G06F2212/1024 , G06F2212/1052 , G06F2212/621 , G06F2212/656
摘要： Managing lowest point of coherency (LPC) memory using a service layer adapter, the adapter coupled to a processor and an accelerator on a host computing system, the processor configured for symmetric multi-processing, including receiving, by the adapter, a memory access instruction from the accelerator; retrieving, by the adapter, a real address for the memory access instruction; determining, using base address registers on the adapter, that the real address targets the LPC memory, wherein the base address registers direct memory access requests between the LPC memory and other memory locations on the host computing system; and sending, by the adapter, the memory access instruction and the real address to a media controller for the LPC memory, wherein the media controller for the LPC memory is attached to the adapter via a memory interface.
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3.发明申请TECHNIQUES FOR IMPLEMENTING BARRIERS TO EFFICIENTLY SUPPORT CUMULATIVITY IN A WEAKLY-ORDERED MEMORY SYSTEM 审中-公开实施障碍以有效支持令人怀疑的记忆系统中的累积性的技术公开(公告)号：US20170046264A1
公开(公告)日：2017-02-16
申请号：US15339191
申请日：2016-10-31
IPC分类号： G06F12/0811 , G06F9/38 , G06F12/0897 , G06F12/0815 , G06F12/0842
CPC分类号： G06F12/0811 , G06F9/30043 , G06F9/30087 , G06F9/3836 , G06F9/3838 , G06F9/522 , G06F12/0815 , G06F12/0842 , G06F12/0897 , G06F12/128 , G06F2212/284 , G06F2212/6042
摘要： A technique for operating a cache memory of a data processing system includes creating respective pollution vectors to track which of multiple concurrent threads executed by an associated processor core are currently polluted by a store operation resident in the cache memory. Dependencies in a dependency data structure of a store queue of the cache memory are set based on the pollution vectors to reduce unnecessary ordering effects. Store operations are dispatched from the store queue in accordance with the dependencies indicated by the dependency data structure.
摘要翻译： 用于操作数据处理系统的高速缓冲存储器的技术包括创建相应的污染向量，以跟踪由相关联的处理器核心执行的多个并发线程当前被驻留在高速缓存存储器中的存储操作所污染的哪一个。 基于污染向量设置缓存存储器的存储队列的依赖性数据结构中的依赖关系，以减少不必要的排序效应。 存储操作根据依赖关系数据结构指示的依赖关系从存储队列中发出。
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公开(公告)号：US20170004004A1
公开(公告)日：2017-01-05
申请号：US14841059
申请日：2015-08-31
CPC分类号： G06F9/467 , G06F12/0811 , G06F12/0828 , G06F12/0833 , G06F12/084 , G06F12/0846 , G06F12/0857 , G06F12/0862 , G06F2212/1016 , G06F2212/60 , G06F2212/6024 , G06F2212/621
摘要： In at least some embodiments, a cache memory of a data processing system receives a transactional memory access request including a target address and a priority of the requesting memory transaction. In response, transactional memory logic detects a conflict for the target address with a transaction footprint of an existing memory transaction and accesses a priority of the existing memory transaction. In response to detecting the conflict, the transactional memory logic resolves the conflict by causing the cache memory to fail the requesting or existing memory transaction based at least in part on their relative priorities. Resolving the conflict includes at least causing the cache memory to fail the existing memory transaction when the requesting memory transaction has a higher priority than the existing memory transaction, the transactional memory access request is a transactional load request, and the target address is within a store footprint of the existing memory transaction.
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公开(公告)号：US20140143613A1
公开(公告)日：2014-05-22
申请号：US13777729
申请日：2013-02-26
发明人： ROBERT A. CARGNONI , JOHN S. DODSON , GUY L. GUTHRIE , WILLIAM J. STARKE , JEFFREY A. STUECHELI
IPC分类号： G06F11/00
CPC分类号： G06F9/38 , G06F9/3824 , G06F9/3842 , G06F9/3859 , G06F11/00 , G06F11/006 , G06F11/1048 , G06F12/0897 , G06F13/16
摘要： In a data processing system, a selection is made, based at least on an access type of a memory access request, between at least a first timing and a second timing of data transmission with respect to completion of error detection processing on a target memory block of the memory access request. In response to receipt of the memory access request and selection of the first timing, data from the target memory block is transmitted to a requestor prior to completion of error detection processing on the target memory block. In response to receipt of the memory access request and selection of the second timing, data from the target memory block is transmitted to the requestor after and in response to completion of error detection processing on the target memory block.
摘要翻译： 在数据处理系统中，至少基于存储器访问请求的访问类型，在关于目标存储器块的错误检测处理完成的数据传输的至少第一定时和第二定时之间进行选择 的内存访问请求。 响应于存储器访问请求的接收和第一定时的选择，在对目标存储器块进行错误检测处理完成之前，来自目标存储器块的数据被发送到请求者。 响应于存储器访问请求的接收和第二定时的选择，来自目标存储器块的数据在对目标存储器块执行错误检测处理之后并且响应于完成对目标存储器块的错误检测处理而被发送到请求者。
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6.发明申请公开(公告)号：US20190332549A1
公开(公告)日：2019-10-31
申请号：US16395976
申请日：2019-04-26
发明人： BARTHOLOMEW BLANER , JEFFREY A. STUECHELI , MICHAEL S. SIEGEL , WILLIAM J. STARKE , CURTIS C. WOLLBRINK , KENNETH M. VALK , LAKSHMINARAYANA ARIMILLI , JOHN D. IRISH
摘要： An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes directory control logic that configures at least a number of congruence classes utilized in the real address-based directory based on configuration parameters specified on behalf of or by the accelerator unit.
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公开(公告)号：US20190220409A1
公开(公告)日：2019-07-18
申请号：US15873366
申请日：2018-01-17
发明人： GUY L. GUTHRIE , MICHAEL S. SIEGEL , WILLIAM J. STARKE , JEFFREY A. STUECHELI , DEREK E. WILLIAMS
IPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0817
摘要： A cache coherent data processing system includes at least non-overlapping first, second, and third coherency domains. A master in the first coherency domain of the cache coherent data processing system selects a scope of an initial broadcast of an interconnect operation from among a set of scopes including (1) a remote scope including both the first coherency domain and the second coherency domain, but excluding the third coherency domain that is a peer of the first coherency domain, and (2) a local scope including only the first coherency domain. The master then performs an initial broadcast of the interconnect operation within the cache coherent data processing system utilizing the selected scope, where performing the initial broadcast includes the master initiating broadcast of the interconnect operation within the first coherency domain.
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公开(公告)号：US20160179592A1
公开(公告)日：2016-06-23
申请号：US14733331
申请日：2015-06-08
CPC分类号： G06F9/546 , G06F9/467 , G06F9/4881 , G06F9/54 , G06F9/544
摘要： In a data processing system, a switch includes a receive data structure including receive entries each uniquely corresponding to a receive window, where each receive entry includes addressing information for one or more mailboxes into which messages can be injected, a send data structure including send entries each uniquely corresponding to a send window, where each send entry includes a receive window field that identifies one or more receive windows, and switch logic. The switch logic, responsive to a request to push a message to one or more receiving threads, accesses a send entry that corresponds to a send window of the sending thread, utilizes contents of the receive window field of the send entry to access one or more of the receive entries, and pushes the message to one or more mailboxes of one or more receiving threads utilizing the addressing information of the receive entry or entries.
摘要翻译： 在数据处理系统中，交换机包括接收数据结构，其包括每个唯一对应于接收窗口的接收条目，其中每个接收条目包括可以注入消息的一个或多个邮箱的寻址信息，包括发送条目的发送数据结构 每个唯一对应于发送窗口，其中每个发送条目包括识别一个或多个接收窗口的接收窗口字段和开关逻辑。 交换机逻辑响应于将消息推送到一个或多个接收线程的请求，访问对应于发送线程的发送窗口的发送条目，利用发送条目的接收窗口字段的内容来访问一个或多个 的接收条目，并且使用接收条目或条目的寻址信息将消息推送到一个或多个接收线程的一个或多个邮箱。
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公开(公告)号：US20150286570A1
公开(公告)日：2015-10-08
申请号：US14472056
申请日：2014-08-28
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F9/30043 , G06F9/30087 , G06F9/3836 , G06F9/3838 , G06F9/522 , G06F12/0815 , G06F12/0842 , G06F12/0897 , G06F12/128 , G06F2212/284 , G06F2212/6042
摘要： A technique for operating a cache memory of a data processing system includes creating respective pollution vectors to track which of multiple concurrent threads executed by an associated processor core are currently polluted by a store operation resident in the cache memory. Dependencies in a dependency data structure of a store queue of the cache memory are set based on the pollution vectors to reduce unnecessary ordering effects. Store operations are dispatched from the store queue in accordance with the dependencies indicated by the dependency data structure.
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公开(公告)号：US20150242320A1
公开(公告)日：2015-08-27
申请号：US14192227
申请日：2014-02-27
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0811 , G06F12/0833 , G06F2212/283 , G06F2212/601 , G06F2212/621
摘要： In some embodiments, in response to execution of a load-reserve instruction that binds to a load target address held in a store-through upper level cache, a processor core sets a core reservation flag, transmits a load-reserve operation to a store-in lower level cache, and tracks, during a core reservation tracking interval, the reservation requested by the load-reserve operation until the store-in lower level cache signals that the store-in lower level cache has assumed responsibility for tracking the reservation. In response to receipt during the core reservation tracking interval of an invalidation signal indicating presence of a conflicting snooped operation, the processor core cancels the reservation by resetting the core reservation flag and fails a subsequent store-conditional operation. Responsive to not canceling the reservation during the core reservation tracking interval, the processor core determines whether a store-conditional operation succeeds by reference to a pass/fail indication provided by the store-in lower level cache.
摘要翻译： 在一些实施例中，响应于绑定到存储在上层高速缓存中的加载目标地址的负载预留指令的执行，处理器核心设置核心预留标志，向存储 - 在低级缓存中，并且在核心预约跟踪间隔期间跟踪由加载备用操作请求的预留，直到存储的较低级缓存信号指示存储的较低级缓存已经承担了跟踪该预留的责任。 响应于在指示存在冲突的窥探操作的无效信号的核心预约跟踪间隔期间的接收，处理器核心通过重置核心预留标志来取消预约，并且使随后的存储条件操作失败。 响应于在核心预约跟踪间隔期间不取消预约，处理器核心通过参考由存储的下级高速缓存提供的通过/失败指示来确定存储条件操作是否成功。
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