-
公开(公告)号：US20180150396A1
公开(公告)日：2018-05-31
申请号：US15364458
申请日：2016-11-30
发明人： ETAI ADAR , LAKSHMINARAYANA B. ARIMILLI , YIFTACH BENJAMINI , BARTHOLOMEW BLANER , WILLIAM J. STARKE , JEFFREY A. STUECHELI
IPC分类号： G06F12/0815 , G06F12/1081 , G06F12/14
CPC分类号： G06F12/0815 , G06F12/1081 , G06F12/145 , G06F13/1668 , G06F2212/1024 , G06F2212/1052 , G06F2212/621 , G06F2212/656
摘要： Managing lowest point of coherency (LPC) memory using a service layer adapter, the adapter coupled to a processor and an accelerator on a host computing system, the processor configured for symmetric multi-processing, including receiving, by the adapter, a memory access instruction from the accelerator; retrieving, by the adapter, a real address for the memory access instruction; determining, using base address registers on the adapter, that the real address targets the LPC memory, wherein the base address registers direct memory access requests between the LPC memory and other memory locations on the host computing system; and sending, by the adapter, the memory access instruction and the real address to a media controller for the LPC memory, wherein the media controller for the LPC memory is attached to the adapter via a memory interface.
-
公开(公告)号：US20180089104A1
公开(公告)日：2018-03-29
申请号：US15806448
申请日：2017-11-08
IPC分类号： G06F12/1081 , G06F13/42 , G06F13/28 , G06F13/40
CPC分类号： G06F12/1081 , G06F13/28 , G06F13/4068 , G06F13/4282 , G06F2212/1016
摘要： Direct memory access between an accelerator and a processor using a coherency adapter including receiving, by the adapter from the accelerator, a request to initiate a DMA transfer; providing, by the adapter, a translation tag (‘XTAG’) to the accelerator; receiving, by the adapter from the accelerator, a DMA instruction comprising the XTAG; generating, by the adapter, a DMA instruction comprising a real address based on the XTAG; and sending, by the adapter, the generated DMA instruction comprising the real address to a communications bus.
-
搜索结果
2 条记录 (耗时 0.013 秒)
