公开(公告)号：US10809612B2

公开(公告)日：2020-10-20

申请号：US16702492

申请日：2019-12-03

申请人： Shanghai Huali Microelectronics Corporation

发明人： Zhigang Chen ,  Junhan Liu

IPC分类号： G03F1/36

摘要： The present invention discloses a design method of a sub resolution assist feature, which comprises the following steps of: S01: forming a sub resolution assist feature in the mask plate, the upper surface of the sub resolution assist feature is aligned with the upper surface of the mask plate; S02: forming a process pattern on one side, which contains the sub resolution assist feature, of the mask plate, the position of the process pattern is not superposed with the sub resolution assist feature in a vertical direction.

公开(公告)号：US20200211667A1

公开(公告)日：2020-07-02

申请号：US16684989

申请日：2019-11-15

申请人： Shanghai Huali Microelectronics Corporation

发明人： Ying Yan ,  Jianming Jin ,  Zheng Gong

IPC分类号： G11C17/18 ,  G11C17/16

摘要： Embodiments described herein relate to an efuse programming unit, an efuse circuit and a programming process thereof. The efuse circuit comprises an efuse programming unit comprising an efuse component and an anti-efuse programming transistor, the anti-efuse programming transistor being connected in parallel with the efuse component, wherein the anti-efuse programming transistor is an electrically programmable device, presents a high-resistance state before programming and presents a low-resistance state after programming, and the efuse component is an electrically programmable device, presents a low-resistance state before programming and presents a high-resistance after programming; and a programming control device connected in series with the efuse programming unit.

公开(公告)号：US10409170B2

公开(公告)日：2019-09-10

申请号：US15800043

申请日：2017-10-31

申请人： Shanghai Huali Microelectronics Corporation

发明人： Qiaoli Chen ,  Zhengkai Yang

IPC分类号： G03F7/20 ,  G03F1/26 ,  G03F1/36 ,  G03F1/50 ,  G03F1/42 ,  G03F1/30

摘要： The present invention discloses a method for quickly establishing lithography process condition by a pre-compensation value, comprising: firstly determining a reference process condition of masks of which parameters are same, and then determining an optimum process condition of the first mask; thereafter, calculating a ratio of the optimum process condition of the first mask deviating from the reference process condition, wherein if the ratio is equal to or larger than a set threshold, the first mask is inspected, and if the ratio is less than the set threshold, an optimum process condition of the second mask is determined according to the ratio and the reference process condition of the second mask; and by analogy, determining optimum process conditions of the rest masks. The method of the present invention can quickly establish a lithograph process condition, reduce the trial production time for determining the optimum defocus amount and exposure amount.

公开(公告)号：US10269893B2

公开(公告)日：2019-04-23

申请号：US15826726

申请日：2017-11-30

申请人： SHANGHAI HUALI MICROELECTRONICS CORPORATION

发明人： Yeqing Cui ,  Ran Huang ,  Jianning Deng

IPC分类号： H01L49/02 ,  H01L21/66 ,  H01L21/321 ,  H01L21/768 ,  H01L21/67 ,  G01R27/26 ,  G01R31/26 ,  H01L23/522 ,  H01L23/528 ,  H01L21/285 ,  H01L21/288

摘要： A method for MOM capacitance value control is disclosed. The method comprises: S01: setting a target thicknesses for each metal layers; S02: after forming a current metal layer, measuring a thickness of the current metal layer; when the thickness of the current metal layer is equal to or less than a threshold value, then turning to step S03; S03: calculating multiple capacitance variations related to the current metal layer according to the thickness of the current metal layer; wherein each of the capacitance variation related to the current metal layer is between an actual capacitance value of a MOM capacitor combination associated with the current metal layer and a target capacitance value of the same MOM capacitor combination; S04: calculating updated target thicknesses for all subsequent metal layers according to the capacitance variations related to the current metal layer.

公开(公告)号：US10261426B2

公开(公告)日：2019-04-16

申请号：US15800071

申请日：2017-11-01

申请人： Shanghai Huali Microelectronics Corporation

发明人： Yunqing Dai ,  Jian Wang

IPC分类号： G03F7/20 ,  H01L21/68 ,  H01L21/66

摘要： An optimization method for overlay error compensation is disclosed. The method comprises setting process parameters for each semiconductor layer of a semiconductor device corresponding to a run path formed by different lithographic apparatus which sequentially process target semiconductor layers from a first target layer to a latest target layer; measuring overlay errors between an actual and a theoretical exposed patterns of the first semiconductor layer; selecting a group of process parameters corresponding to the run path from the first target layer to the latest target layer aligned by the current semiconductor layer; after exposing the current semiconductor layer using the selected process parameters, measuring overlay errors between the current semiconductor layer and its target layer; and correcting the selected process parameters according to the overlay errors between the current semiconductor layer and its target layer, and the overlay errors between the actual and theoretical exposed patterns of the first semiconductor layer.

公开(公告)号：US10134900B2

公开(公告)日：2018-11-20

申请号：US15390528

申请日：2016-12-25

申请人： SHANGHAI HUALI MICROELECTRONICS CORPORATION

发明人： Qiuming Huang ,  Jun Tan ,  Qiang Yan

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/165 ,  H01L29/49 ,  H01L29/04 ,  H01L29/06 ,  H01L29/40 ,  H01L21/02 ,  H01L21/306

摘要： A structure of SiGe source/drain and a preparation method thereof are disclosed in the present invention. Firstly, providing a semiconductor single crystal silicon substrate. Secondly, etching the semiconductor single crystal silicon substrate to form recesses on both sides of the gate. Thirdly, epitaxially growing a SiGe seed layer and a SiGe bulk layer in the recesses in turn. Fourthly, subjecting the SiGe bulk layer to a crystal plane treatment with a mixed-gases. Fifthly, epitaxially growing a lattice change layer on the SiGe bulk layer. Finally, epitaxially growing a cap layer on the lattice change layer. The preparation method of the present invention can greatly improve the morphology of the SiGe epitaxy in the incomplete Un-tuck structure, and promote the formation of the subsequent metal silicide (NiSi), so that problems such as abnormal resistance and leakage of active area (AA leakage) can be effectively prevented.

公开(公告)号：US10083266B2

公开(公告)日：2018-09-25

申请号：US15283286

申请日：2016-09-30

申请人： SHANGHAI HUALI MICROELECTRONICS CORPORATION

发明人： Yun Cao ,  Huan Kan ,  Fang Wei ,  Jun Zhu ,  Yukun Lv ,  Xusheng Zhang

IPC分类号： G06F17/50 ,  H01L21/768

CPC分类号： G06F17/504 ,  G06F2217/16 ,  H01L21/3212 ,  H01L21/76819

摘要： A simulation method of CMP process comprises: building a CMP model, and forming a matrix table of line width logarithm-density according to the CMP model, and making each intersection of the matrix table correspond to each CMP result under the corresponding line width and density; dividing a layout into a plurality of grids, and converting the equivalent line width and density of each grid into the coordinate of line width logarithm-density in the matrix table; fitting and calculating preliminary CMP simulation results of each grid according to the coordinate of each grid in the matrix table and the CMP simulation results of its adjacent intersections of the matrix table; fitting and computing final CMP simulation results of each grid according to a related weighting factor which considers the impact of adjacent grids for the current grid on the layout; outputting the final CMP simulation results of the whole layout.

公开(公告)号：US20180175195A1

公开(公告)日：2018-06-21

申请号：US15429194

申请日：2017-02-10

申请人： Shanghai Huali Microelectronics Corporation

发明人： Qiuming Huang

IPC分类号： H01L29/78 ,  H01L21/306 ,  H01L21/02 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/167 ,  H01L27/11

CPC分类号： H01L29/7848 ,  H01L21/02181 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28185 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L27/1104 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66636

摘要： A method of embedding SiGe when fabricating a PMOS device is provided. Multiple layers of SiGe layers with different Ge contents may be formed such that the Ge content increases to from bottom layer(s) to middle layer(s), and decreases from the middle layer(s) to top layer(s). In some embodiments, the embedded SiGe can have a SiGe seed layer over a substrate, a first SiGe transition layer over the SiGe seed layer, a SiGe milled layer over the first SiGe transition layer, and a second SiGe transition layer over the SiGe middle layer. The first SiGe transition layer can have a Ge content increasing from a bottom of the first SiGe transition layer to a top of the first SiGe transition layer. The second SiGe transition layer can have a Ge content decreasing from a bottom of the second SiGe transition layer to a top of the second SiGe transition layer.

公开(公告)号：US20180175157A1

公开(公告)日：2018-06-21

申请号：US15429192

申请日：2017-02-10

申请人： Shanghai Huali Microelectronics Corporation

发明人： Yingming Liu ,  Yu Bao ,  Haifeng Zhou ,  Jingxun Fang

IPC分类号： H01L29/51 ,  H01L29/423 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/517 ,  H01L21/28185 ,  H01L21/28229 ,  H01L29/49 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/78

摘要： The present disclosure addresses and solves the current problem of oxygen accumulation in IL after an HKMG stack is formed. A fabrication method is provided for fabricating high-k/metal gate semiconductor device by forming at least one Titanium (Ti) layer between multiple HK layers. A high-k/metal gate semiconductor device including at least one TiO2 layer between multiple HK layers is also provided.

公开(公告)号：US20180174924A1

公开(公告)日：2018-06-21

申请号：US15429195

申请日：2017-02-10

申请人： Shanghai Huali Microelectronics Corporation

发明人： Tong Lei ,  Yongyue Chen ,  Haifeng Zhou

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/02 ,  H01L21/321 ,  H01L21/033

CPC分类号： H01L21/823828 ,  H01L21/02115 ,  H01L21/02167 ,  H01L21/0332 ,  H01L21/3212 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/66545

摘要： One aspect of the present disclosure is a method of fabricating metal gate by forming special layers in place of traditional TiN hard mask over the ILD0 layer to avoid ILD0 losses due to conventional ILD0 CMP. The method can comprise: after the ILD0 CMP, forming a first thin ashable film layer over the ILD0 layer; then forming a second thin dielectric layer over the first layer; during the aluminum CMP process for a first region (PMOS or NMOS), removing the second layer through polishing until the top surface of the first ashable film layer; and then removing first ashable film layer through an ashing method such as burning. In this way, ILD0 loss can be reduced during the first aluminum CMP step and thus can reduce initial height of ILD0, which in turn can reduce the height of initial dummy gate filled in the cavity.