公开(公告)号：US10651285B2

公开(公告)日：2020-05-12

申请号：US15429192

申请日：2017-02-10

申请人： Shanghai Huali Microelectronics Corporation

发明人： Yingming Liu ,  Yu Bao ,  Haifeng Zhou ,  Jingxun Fang

IPC分类号： H01L29/51 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49

摘要： The present disclosure addresses and solves the current problem of oxygen accumulation in IL after an HKMG stack is formed. A fabrication method is provided for fabricating high-k/metal gate semiconductor device by forming at least one Titanium (Ti) layer between multiple HK layers. A high-k/metal gate semiconductor device including at least one TiO2 layer between multiple HK layers is also provided.

公开(公告)号：US20160300758A1

公开(公告)日：2016-10-13

申请号：US14753311

申请日：2015-06-29

申请人： Shanghai Huali Microelectronics Corporation

发明人： Tong Lei ,  Jingxun Fang

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/285

CPC分类号： H01L21/76829 ,  H01L21/02274 ,  H01L21/28562 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76883 ,  H01L2221/1047

摘要： The present invention provides a method for forming a cobalt barrier layer and a metal interconnection process. The method is performed on a surface of a semiconductor device substrate on which metal interconnection lines and an inter-line dielectric layer are formed, and comprises: depositing a dielectric material film on a surface of the inter-line dielectric layer by atomic layer deposition, to densify the surface of the inter-line dielectric layer; removing the deposited dielectric material film, to expose the metal interconnection lines and the densified surface of the inter-line dielectric layer; selectively depositing cobalt on surfaces of the metal interconnection lines to form a cobalt barrier layer. In the present invention, deposition selectivity of cobalt on surfaces of the metal interconnection lines and the inter-line dielectric layer is improved, thus reducing leakage current between metal interconnection lines and improving yield and reliability of the product.

摘要翻译： 本发明提供一种形成钴阻挡层和金属互连工艺的方法。 该方法在其上形成有金属互连线和线间电介质层的半导体器件基板的表面上进行，并且包括：通过原子层沉积在电介体层的表面上沉积介电材料膜， 以致致密化该线间电介质层的表面; 去除沉积的介电材料膜，暴露金属互连线和线间电介质层的致密化表面; 在金属互连线的表面上选择性地沉积钴以形成钴阻挡层。 在本发明中，钴在金属互连线和线间电介质层的表面上的沉积选择性提高，从而减少金属互连线之间的漏电流并提高产品的产量和可靠性。

公开(公告)号：US08987101B2

公开(公告)日：2015-03-24

申请号：US14040736

申请日：2013-09-30

申请人： Shanghai Huali Microelectronics Corporation

发明人： Yi Ding ,  Minghua Zhang ,  Jingxun Fang ,  Junhua Yan

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L29/66795 ,  H01L21/02428 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/02658 ,  H01L29/7848 ,  H01L29/785

摘要： A method of forming strained source and drain regions in a P-type FinFET structure is disclose. The method comprises depositing an isolation layer on the FinFET structure; applying a lithography and etching process to expose the isolation layer in two areas on opposite sides of the gate over the source/drain region of the FinFET, and etching through the exposed isolation layer to expose the semiconductive material of the source/drain region in the two areas; forming a recess in each of the source/drain region from the exposed semiconductive material; selectively epitaxially growing another semiconductive material in the recesses to increase the source/drain strain; and removing the rest of the isolation layer.

摘要翻译： 公开了一种在P型FinFET结构中形成应变源极和漏极区域的方法。 该方法包括在FinFET结构上沉积隔离层; 施加光刻和蚀刻工艺以在FinFET的源极/漏极区域上的栅极的相对侧上的两个区域中暴露隔离层，并且通过暴露的隔离层蚀刻以暴露出源极/漏极区域的半导体材料 两个区域 在所述源极/漏极区域中的每一个中从所述暴露的半导体材料形成凹部; 在凹槽中选择性地外延生长另一种半导体材料以增加源极/漏极应变; 并去除隔离层的其余部分。

公开(公告)号：US09449872B1

公开(公告)日：2016-09-20

申请号：US14753311

申请日：2015-06-29

申请人： Shanghai Huali Microelectronics Corporation

发明人： Tong Lei ,  Jingxun Fang

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L21/285 ,  H01L21/02

CPC分类号： H01L21/76829 ,  H01L21/02274 ,  H01L21/28562 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76883 ,  H01L2221/1047

摘要： The present invention provides a method for forming a cobalt barrier layer and a metal interconnection process. The method is performed on a surface of a semiconductor device substrate on which metal interconnection lines and an inter-line dielectric layer are formed, and comprises: depositing a dielectric material film on a surface of the inter-line dielectric layer by atomic layer deposition, to densify the surface of the inter-line dielectric layer; removing the deposited dielectric material film, to expose the metal interconnection lines and the densified surface of the inter-line dielectric layer, selectively depositing cobalt on surfaces of the metal interconnection lines to form a cobalt barrier layer. In the present invention, deposition selectivity of cobalt on surfaces of the metal interconnection lines and the inter-line dielectric layer is improved, thus reducing leakage current between metal interconnection lines and improving yield and reliability of the product.

摘要翻译： 本发明提供一种形成钴阻挡层和金属互连工艺的方法。 该方法在其上形成有金属互连线和线间电介质层的半导体器件基板的表面上进行，并且包括：通过原子层沉积在电介体层的表面上沉积介电材料膜， 以致致密化该线间电介质层的表面; 去除沉积的介电材料膜，暴露金属互连线和线间电介质层的致密化表面，在金属互连线的表面上选择性地沉积钴以形成钴阻挡层。 在本发明中，钴在金属互连线和线间电介质层的表面上的沉积选择性提高，从而减少金属互连线之间的漏电流并提高产品的产量和可靠性。

公开(公告)号：US08673768B2

公开(公告)日：2014-03-18

申请号：US13730103

申请日：2012-12-28

申请人： Shanghai Huali Microelectronics Corporation

发明人： Jingxun Fang ,  Chuanmin Zhang ,  Wei Zuo ,  Xiaogang Tong ,  Zhe Wang ,  Lei Deng ,  Jing Wen

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fabrication method for improving surface planarity after tungsten chemical mechanical polishing (W-CMP) is disclosed. The method forms contact holes and dummy patterns by performing two respective photolithography-and-etching processes to ensure that the dummy patterns have a depth smaller than that of the contact holes. Then the method fills tungsten into the contact holes and dummy patterns and removes the redundant tungsten by a W-CMP process. With such a method, difference of wiring density between areas can be reduced by the dummy patterns, and hence a better surface planarity of the contact hole layer can be achieved. Besides, as the dummy patterns are formed in a pre-metal dielectric layer and their depth is well controlled, tungsten filled in the dummy patterns will not contact with the device area below the pre-metal dielectric layer, and thus will not affect the performance of the device.

摘要翻译： 公开了一种用于改善钨化学机械抛光（W-CMP）之后的表面平面度的制造方法。 该方法通过执行两个相应的光刻和蚀刻工艺来形成接触孔和虚拟图案，以确保虚拟图案的深度小于接触孔的深度。 然后，该方法将钨填充到接触孔和虚拟图案中，并通过W-CMP工艺去除冗余钨。 通过这种方法，可以通过虚拟图案来减小区域之间的布线密度的差异，因此可以实现接触孔层的更好的表面平面度。 此外，由于在预金属介电层中形成虚拟图案并且其深度被很好地控制，填充在虚设图案中的钨将不会与预金属介电层下方的器件区域接触，因此不会影响性能 的设备。

公开(公告)号：US20180175157A1

公开(公告)日：2018-06-21

申请号：US15429192

申请日：2017-02-10

申请人： Shanghai Huali Microelectronics Corporation

发明人： Yingming Liu ,  Yu Bao ,  Haifeng Zhou ,  Jingxun Fang

IPC分类号： H01L29/51 ,  H01L29/423 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/517 ,  H01L21/28185 ,  H01L21/28229 ,  H01L29/49 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/78

摘要： The present disclosure addresses and solves the current problem of oxygen accumulation in IL after an HKMG stack is formed. A fabrication method is provided for fabricating high-k/metal gate semiconductor device by forming at least one Titanium (Ti) layer between multiple HK layers. A high-k/metal gate semiconductor device including at least one TiO2 layer between multiple HK layers is also provided.

公开(公告)号：US08645879B2

公开(公告)日：2014-02-04

申请号：US13731128

申请日：2012-12-31

申请人： Shanghai Huali Microelectronics Corporation

发明人： Jingxun Fang ,  Hsusheng Chang ,  Yungchieh Fan

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： The present invention disclosed an algorithm of Cu interconnect dummy inserting, including: divide the surface of semiconductor chip into several square windows with an area of A, each of which is non-overlap; perform a logic operation on each square window; and divide the window into two parts: {circle around (1)} the area to-be-inserted; {circle around (2)} the non-inserting area; determine the metal density of the dummy pattern that should be inserted to each square window and the line width; determine the dummy pattern that should be inserted to the windows according to the metal density, line width, the pre-set dummy pattern and the layouting rules. The beneficial effects of the present invention is: avoided the shortcomings of fill density maximization in the rule-based filling method by using reasonable metal density and line width. And with a combination of the influence of line width and density to the copper plating process and chemical mechanical polishing morphology in model-based filling method, it can achieve a better planarization effect.

摘要翻译： 本发明公开了一种Cu互连虚拟插入算法，包括：将半导体芯片的表面划分成几个方形窗口，其面积为A，每个窗口不重叠; 对每个方形窗口执行逻辑运算; 并将窗口分为两部分：{circle around（1）}要插入的区域; {round around（2）}非插入区域; 确定应插入每个正方形窗口的虚拟图案的金属密度和线宽度; 根据金属密度，线宽，预设的伪图案和布局规则确定应插入窗口的虚拟图案。 本发明的有益效果是：通过使用合理的金属密度和线宽，避免了基于规则的填充方法中填充密度最大化的缺点。 并结合线宽和密度对铜电镀工艺和化学机械抛光形态的影响，在基于模型的填充方法中，可以实现更好的平坦化效果。