Abstract:
A memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. The steering element and state change element are disposed in a vertically-oriented pillar. Other aspects are also provided.
Abstract:
There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
Abstract:
A method for reliable deactivation of a security (EAS) tag, and an apparatus for accomplishing the same. The method generally includes placing a security tag a first distance from a deactivation apparatus; determining whether a deactivation confirmation signal has occurred; and when it is determined that the deactivation confirmation signal did not occur, placing the security tag closer to the deactivation apparatus. The deactivation apparatus generally includes a pad configured to transmit a deactivation pulse having a power sufficient to deactivate the security tag when it is within a deactivation field; a tag reader configured to detect a signal transmission from an active tag when it is in a read field of the deactivation apparatus; a confirmation indicator configured to indicate that the pad has sent the deactivation pulse; and logic configured to determine when an active tag is in the deactivation field or the read field, and communicate to the confirmation indicator that the pad has sent the deactivation pulse.
Abstract:
A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
Abstract:
The invention relates to bar compositions comprising thermochromatic pigment or dye signaling temperature and/or benefit agent release. In a preferred embodiment, the pigment is introduced in the form of a separate domain (e.g., separate chips) which separate chip or chips is combined with a surfactant-containing chips to form the final bar.
Abstract:
The invention relates to method of signaling temperature and/or benefit agent release using bar compositions comprising thermochromatic pigment or dye. In a preferred embodiment, the pigment is introduced in the form of a separate domain (e.g., separate chips) which separate chip or chips is combined with a surfactant-containing chips to form the final bar.
Abstract:
A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
Abstract:
Metallic nanoparticles are provided which can be used in forming metallic film conductors at reduced temperatures compatible with plastic carriers for the film conductors. This is realized by using a lower molecular weight organic encapsulant of the nanoparticle and thereby reducing the temperature at which the organic encapsulant evaporates. Further, the sintering or melting temperature of the metallic nanoparticle is reduced by using a lower sized nanoparticle, thereby increasing the particle surface area relative to the particle volume and thus reducing the required heat and melting temperature of the particle.