公开(公告)号：US11950432B2

公开(公告)日：2024-04-02

申请号：US17362936

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiang-Ku Shen ,  Ku-Feng Lin ,  Liang-Wei Wang ,  Dian-Hau Chen

IPC: H10B61/00 ,  G11C11/16 ,  H01L23/522 ,  H01L23/528 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80

CPC classification number: H10B61/22 ,  G11C11/161 ,  H01L23/5226 ,  H01L23/5283 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80

Abstract: A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first semiconductor substrate, a first bonding structure and a memory cell. The second semiconductor device is stacked over the first semiconductor device. The second semiconductor device includes a second semiconductor substrate, a second bonding structure in a second dielectric layer and a peripheral circuit between the second semiconductor substrate and the second bonding structure. The first bonding structure and the second bonding structure are bonded and disposed between the memory cell and the peripheral circuit, and the memory cell and the peripheral circuit are electrically connected through the first bonding structure and the second bonding structure.

公开(公告)号：US20240087617A1

公开(公告)日：2024-03-14

申请号：US18518578

申请日：2023-11-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin

IPC: G11C7/06

CPC classification number: G11C7/06

Abstract: A memory device that includes a first memory cell, a second memory cell and a sense amplifier. The sense amplifier includes a first branch and a second branch and are configured to output a first voltage and a second voltage to the first memory and the second memory, respectively in a trimming operation. A first clamp device of the sense amplifier includes a first clamp transistor and a plurality of first trimming transistors that are coupled to the first clamp transistor in parallel. The gate terminals of the first clamp transistor and the plurality of first trimming transistors are biased by a fixed clamp voltage. Each of the plurality of first trimming transistors is selectively conducted to compensate a mismatch between the first voltage and the second voltage.

公开(公告)号：US11910723B2

公开(公告)日：2024-02-20

申请号：US17032638

申请日：2020-09-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  G11C11/1655 ,  G11C11/1657 ,  H10B61/22 ,  H10N50/01

Abstract: A memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, each row of memory cells being associated with a word line, each column of memory cells being associated with a bit line and a source line. Each memory cell includes: a storage device coupled to the bit line, the storage device being selectable between a first resistance state and a second resistance state in response to a bit line signal at the bit line; and a selection device connected in series with the storage device and coupled to the source line, the selection device being configured to provide access to the storage device in response to a word line signal at the word line. The memory device further includes a word-line driver and a bit-line driver. A first number of the source lines are connected in parallel.

公开(公告)号：US11810635B2

公开(公告)日：2023-11-07

申请号：US18163461

申请日：2023-02-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin ,  Jui-Che Tsai ,  Perng-Fei Yuh ,  Yih Wang

IPC: G11C7/06 ,  H03K3/356 ,  H01L27/06 ,  H03K3/037

CPC classification number: G11C7/065 ,  H01L27/0629 ,  H03K3/037 ,  H03K3/35613

Abstract: A sense amplifier including a first input transistor having a first input gate and a first drain/source terminal, a second input transistor having a second input gate and a second drain/source terminal, a latch circuit, and a first capacitor. The latch circuit includes a first latch transistor having a third drain/source terminal connected to the first drain/source terminal and a second latch transistor having a fourth drain/source terminal connected to the second drain/source terminal. The first capacitor is connected on one side to the first input gate and on another side to the fourth drain/source terminal to reduce a coupling effect in the sense amplifier.

公开(公告)号：US20230179186A1

公开(公告)日：2023-06-08

申请号：US18163461

申请日：2023-02-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin ,  Jui-Che Tsai ,  Perng-Fei Yuh ,  Yih Wang

IPC: H03K3/037 ,  H01L27/06 ,  H03K3/356 ,  G11C7/06

CPC classification number: H03K3/037 ,  H01L27/0629 ,  H03K3/35613 ,  G11C7/065

Abstract: A sense amplifier including a first input transistor having a first input gate and a first drain/source terminal, a second input transistor having a second input gate and a second drain/source terminal, a latch circuit, and a first capacitor. The latch circuit includes a first latch transistor having a third drain/source terminal connected to the first drain/source terminal and a second latch transistor having a fourth drain/source terminal connected to the second drain/source terminal. The first capacitor is connected on one side to the first input gate and on another side to the fourth drain/source terminal to reduce a coupling effect in the sense amplifier.

公开(公告)号：US20230123830A1

公开(公告)日：2023-04-20

申请号：US18084570

申请日：2022-12-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin

IPC: G11C7/06

Abstract: A memory device that includes a first memory cell, a second memory cell and a sense amplifier. The sense amplifier includes a first branch and a second branch and are configured to output a first voltage and a second voltage to the first memory and the second memory, respectively in a trimming operation. A first clamp device of the sense amplifier includes a first clamp transistor and a plurality of first trimming transistors that are coupled to the first clamp transistor in parallel. The gate terminals of the first clamp transistor and the plurality of first trimming transistors are biased by a fixed clamp voltage. Each of the plurality of first trimming transistors is selectively conducted to compensate a mismatch between the first voltage and the second voltage.

公开(公告)号：US20230037696A1

公开(公告)日：2023-02-09

申请号：US17587242

申请日：2022-01-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin ,  Perng-Fei Yuh ,  Meng-Sheng Chang

IPC: G11C17/16

Abstract: In some aspects of the present disclosure, a memory circuit is disclosed. In some aspects, the memory circuit includes a first storage element coupled to a first bit line, a first transistor coupled between the first storage element and a center node, a second storage element coupled to a second bit line, a second transistor coupled between the second storage element and the center node, and a third transistor coupled between the center node and a reference node.

公开(公告)号：US11575387B2

公开(公告)日：2023-02-07

申请号：US16709622

申请日：2019-12-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Win-San Khwa ,  Hiroki Noguchi ,  Ku-Feng Lin

IPC: H03M7/04 ,  H03M7/16 ,  G11C11/16 ,  H03K19/20

Abstract: An encode apparatus and an encode method may be provided. The encoding apparatus may comprise a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output comprising the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage may produce a second output comprising the converted first input and the converted second input.

公开(公告)号：US20220285434A1

公开(公告)日：2022-09-08

申请号：US17362936

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiang-Ku Shen ,  Ku-Feng Lin ,  Liang-Wei Wang ,  Dian-Hau Chen

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L23/522 ,  H01L23/528 ,  G11C11/16

Abstract: A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first semiconductor substrate, a first bonding structure and a memory cell. The second semiconductor device is stacked over the first semiconductor device. The second semiconductor device includes a second semiconductor substrate, a second bonding structure in a second dielectric layer and a peripheral circuit between the second semiconductor substrate and the second bonding structure. The first bonding structure and the second bonding structure are bonded and disposed between the memory cell and the peripheral circuit, and the memory cell and the peripheral circuit are electrically connected through the first bonding structure and the second bonding structure.

公开(公告)号：US11250908B2

公开(公告)日：2022-02-15

申请号：US16544309

申请日：2019-08-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Der Chih ,  Chia-Fu Lee ,  Yi-Chun Shih ,  Hon-Jarn Lin ,  Ku-Feng Lin

IPC: G11C11/56 ,  G11C11/16

Abstract: A method for sensing logical states of memory cells in multiple segments in a memory device, each cell having a high- and low-resistance state, resulting in different cell current levels for the different resistance states. The method includes determining target reference current levels for the respective segments, at least two of the target reference current levels being different from each other; generating a reference current for each segment with the target reference current level for that segment; comparing the cell current level for each cell to the reference current level for the segment the cell is in; and determining the logical states of the memory cells based on the comparison.