公开(公告)号：US10203570B2

公开(公告)日：2019-02-12

申请号：US15561185

申请日：2017-04-07

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long

IPC: H01L27/12 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368

Abstract: An array substrate, a display panel and a display device are disclosed. The array substrate includes: a plurality of gate lines, a plurality of data lines, and a plurality of common electrodes disposed on a base substrate. The plurality of gate lines are extended in a first direction, the plurality of data lines are extended in a second direction. Each of the common electrodes includes an overlap section which overlaps at least one of the data lines in a direction perpendicular to the base substrate. A gap is provided between the overlap sections of two adjacent common electrodes in the second direction, the two adjacent common electrodes overlap the same data lines in the direction perpendicular to the base substrate. An intersection of the data line and the gate line between the two adjacent common electrodes is located within the gap.

公开(公告)号：US10096663B2

公开(公告)日：2018-10-09

申请号：US14785777

申请日：2015-03-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zheng Liu ,  Xiaoyong Lu ,  Xiaolong Li ,  Chien Hung Liu ,  Chunping Long

IPC: H01L27/12 ,  H01L27/32 ,  H01L51/52 ,  H01L51/56

Abstract: A manufacturing method of an array substrate, an array substrate and a display device are provided. The manufacturing method of the array substrate comprises: forming a first conductive thin film (100) on a base substrate (1); and patterning the first conductive thin film (100), to form a pattern of a cathode (11) on a first region (11) of the base substrate (1), and form a pattern of a gate electrode (4) on a second region (12) of the base substrate (1). Complexity and process time of a fabrication process of an array substrate can be reduced, a fabrication process of an organic electroluminescent panel can be simplified, and production cost can be reduced, by forming a cathode layer of a light-emitting diode and a gate electrode layer of a thin film transistor in different regions of the base substrate at the same time by one patterning process.

公开(公告)号：US09947697B2

公开(公告)日：2018-04-17

申请号：US14769891

申请日：2014-09-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long ,  Yinan Liang ,  Zheng Liu ,  Zuqiang Wang ,  Xueyan Tian

IPC: H01L27/12 ,  H01L27/32

CPC classification number: H01L27/1288 ,  H01L27/1255 ,  H01L27/3262 ,  H01L2227/323

Abstract: The present disclosure provides a low temperature polycrystalline silicon field effect TFT array substrate and a method for producing the same and a display apparatus. The method: using a stepped photo resist process to form a polycrystalline silicon active layer and a lower polar plate of a polycrystalline silicon storage capacitor simultaneously on a substrate in one lithographic process; forming a gate insulation layer on the polycrystalline silicon active layer and the lower polar plate of the polycrystalline silicon storage capacitor; forming a metal layer on the gate insulation layer and etching the metal layer to form a gate electrode and gate lines connected with the gate electrode, a source electrode, a drain electrode and data lines connected with the source electrode and the drain electrode; forming a passivation layer, a photo resist layer and a pixel electrode layer in sequence and patterning the passivation layer, the photo resist layer and the pixel electrode layer to form patterns of an interlayer insulation layer via hole and a pixel electrode in one lithographic process; forming a pixel definition layer on the pixel electrode. The present disclosure may reduce times of lithographic processes for the low temperature polycrystalline silicon field effect TFT array substrate, improve the yield and reduce the costs.

公开(公告)号：US20170294345A1

公开(公告)日：2017-10-12

申请号：US15512372

申请日：2016-03-03

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xiaoyong Lu ,  Hongwei Tian ,  Yueping Zuo ,  Xiaowei Xu ,  Wenqing Xu ,  Chunping Long

IPC: H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/02063 ,  H01L21/0228 ,  H01L21/02315 ,  H01L21/67 ,  H01L21/76814

Abstract: Provided are a method and an apparatus for manufacturing a semiconductor device. The method comprises: forming a first wiring layer on a base substrate; forming an interlayer dielectric layer on the first wiring layer, with contact holes being provided in the interlayer dielectric layer; subjecting bottoms of the contact holes to a dry cleaning process; and forming a second wiring layer on the interlayer dielectric layer, wherein the second wiring layer is electrically connected to the first wiring layer via the contact holes.

公开(公告)号：US09761731B2

公开(公告)日：2017-09-12

申请号：US14764307

申请日：2014-12-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long ,  Yinan Liang

IPC: H01L27/14 ,  H01L29/786 ,  H01L27/12 ,  H01L21/02 ,  H01L21/027 ,  H01L21/265 ,  H01L21/283 ,  H01L21/3065 ,  H01L23/31 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L21/3213 ,  H01L27/32

CPC classification number: H01L29/78675 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0273 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/32139 ,  H01L23/3171 ,  H01L27/12 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1288 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/4958 ,  H01L29/66757 ,  H01L29/786 ,  H01L29/78618 ,  H01L29/78633 ,  H01L2227/323

Abstract: A thin film transistor and its manufacturing method, an array substrate and its manufacturing method, and a display device are provided. The thin film transistor includes a gate electrode, a source electrode, a drain electrode, an active layer and a gate insulation layer. The gate insulation layer is provided above the active layer, the gate, the source electrode and the drain electrode are provided on a same layer above the gate insulation layer, the active layer and the source electrode are connected through a first connection electrode, and the active layer and the drain electrode are connected through a second connection electrode. The thin film transistor can be formed by three times of patterning processes, by which the process time period is shortened, the process yield is improved, and the process cost is reduced, and so on.

公开(公告)号：US20160343780A1

公开(公告)日：2016-11-24

申请号：US14914350

申请日：2015-11-19

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yidong Guo ,  Chunping Long

IPC: H01L27/32 ,  H01L21/02 ,  H01L31/18 ,  H01L29/786 ,  H01L51/00 ,  H01L31/075 ,  H01L29/66

CPC classification number: H01L27/3227 ,  H01L27/142 ,  H01L27/3244 ,  H01L31/068 ,  H01L31/1804 ,  H01L51/0097 ,  H01L2227/323 ,  H01L2227/326 ,  H01L2251/5338 ,  Y02E10/547 ,  Y02P70/521

Abstract: An array substrate, a fabrication method thereof, and an organic light-emitting diode display device are provided; the array substrate (10) comprises a base substrate (100), the base substrate (100) including a display region (102) and a peripheral region (101) surrounding the display region (102), the display region (102) including: a plurality of data lines (12) and a plurality of gate lines (11) intersecting with each other, a plurality of pixel regions (21), formed in a matrix and defined by the plurality of data lines (12) and the plurality of gate lines (11) intersecting with each other formed on the base substrate (100), wherein a thin film transistor (32) is formed in each of the plurality of pixel regions (21); and further, the array substrate (10) also comprises at least one solar cell unit (31), which, together with the thin film transistor (32), is located on a same side of the base substrate (100), and is formed in at least one of the plurality of pixel regions (21) and the peripheral region (101).

Abstract translation: 提供阵列基板，其制造方法和有机发光二极管显示装置; 所述阵列基板（10）包括基底（100），所述基底基板（100）包括显示区域（102）和围绕所述显示区域（102）的外围区域（101），所述显示区域（102）包括： 多个数据线（12）和多条相互交叉的栅极线（11），由矩阵形成并由多条数据线（12）定义的多个像素区域（21） 形成在基板（100）上的彼此相交的栅极线（11），其中在所述多个像素区域（21）的每一个中形成薄膜晶体管（32）。 此外，阵列基板（10）还包括至少一个与薄膜晶体管（32）一起位于基底（100）的同一侧上的太阳能电池单元（31），并形成 在多个像素区域（21）和外围区域（101）中的至少一个中。

公开(公告)号：US20240281101A1

公开(公告)日：2024-08-22

申请号：US18636496

申请日：2024-04-16

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long

IPC: G06F3/044 ,  G06F3/041 ,  G09G3/3233

CPC classification number: G06F3/0446 ,  G06F3/0412 ,  G06F2203/04112 ,  G09G3/3233 ,  G09G2300/0426 ,  G09G2300/0842

Abstract: A touch structure, a touch display panel and an electronic apparatus are provided. The touch structure includes a first touch electrode extended along a first direction and a second touch electrode extended along a second direction; the first touch electrode includes first electrode main body portions in a first conductive layer and a first connection portion in a second conductive layer; the second touch electrode includes second electrode main body portions and a second connection portion in the first conductive layer; the first connection portion is overlapped with the second connection portion in a direction perpendicular to the first conductive layer; the first conductive layer includes first metal meshes formed by first metal lines. The touch structure also includes a dummy electrode in the second conductive layer. The dummy electrode is coupled with at least one of the first connection portion and the second connection portion.

公开(公告)号：US20240072039A1

公开(公告)日：2024-02-29

申请号：US17897302

申请日：2022-08-29

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long ,  Yong Qiao ,  Xinyin Wu

IPC: H01L27/02 ,  H01L27/12

CPC classification number: H01L27/027 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/127

Abstract: Provided an electrostatic protection circuit. The electrostatic protection circuit includes: at least one first transistor and at least one second transistor. A gate electrode and a first electrode of the first transistor are connected to a first signal line, and a second electrode of the first transistor is connected to a second signal line. A gate electrode and a first electrode of the second transistor are connected to the second signal line, and a second electrode of the second transistor is connected to the first signal line. Orthographic projection(s) of a channel and/or a first electrode of the first transistor on a main surface of the array substrate is/are within an orthographic projection of the first signal line on the main surface of the array substrate.

公开(公告)号：US11837609B2

公开(公告)日：2023-12-05

申请号：US17889528

申请日：2022-08-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping Long

IPC: H01L27/12 ,  H01L27/02 ,  G02F1/1362 ,  G09G3/20

CPC classification number: H01L27/124 ,  G02F1/136286 ,  H01L27/0248 ,  G09G3/20 ,  G09G2330/04

Abstract: An Electro-Static Discharge (ESD) protection circuit including a Thin Film Transistor (TFT) arranged between a to-be-protected signal line and a discharging line is provided, wherein a length direction of a channel of the TFT is parallel to an extension direction of the to-be-protected signal line. A display panel and a display device are also provided.

公开(公告)号：US20230162639A1

公开(公告)日：2023-05-25

申请号：US18095166

申请日：2023-01-10

Applicant: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD. ,  BOE Technology Group Co., Ltd.

Inventor： Jianbo Xian ,  Chunping Long ,  Hui Li ,  Yong Qiao

IPC: G09G3/20

CPC classification number: G09G3/20 ,  G09G2300/0809 ,  G09G2310/0286

Abstract: The present disclosure relates to a driving unit, including a first driving sub-circuit, a second driving sub-circuit, and a driving control circuit. The first driving sub-circuit includes first switching elements, configured to output a first signal to the driving unit in response to a control signal from the driving control circuit. The second driving sub-circuit includes one or more second switching elements, and at least one of the second switching elements is configured to output a second signal to the driving unit in response to the control signal. The driving control circuit is configured to output the control signal at a control signal output terminal. Each of the first switching elements and second switching elements includes a transistor. Control signal input terminals of the first switching elements are coupled to the control signal output terminal through a control signal input line having a ring structure.