公开(公告)号：US20090175083A1

公开(公告)日：2009-07-09

申请号：US11684035

申请日：2007-03-09

Applicant: Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

Inventor： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/3436

Abstract: The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.

Abstract translation: 非易失性半导体存储器技术领域本发明涉及一种非易失性半导体存储器，更具体地涉及一种具有增加的程序吞吐量的非易失性半导体存储器。 本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

公开(公告)号：US20080137429A1

公开(公告)日：2008-06-12

申请号：US11971887

申请日：2008-01-09

Applicant: Masaaki TERASAWA ,  Yoshiki Kawajiri ,  Takanori Yamazoe

Inventor： Masaaki TERASAWA ,  Yoshiki Kawajiri ,  Takanori Yamazoe

IPC: G11C16/06

CPC classification number: G11C16/0466 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32

Abstract: A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.

Abstract translation: 从非易失性存储器的低功耗模式的释放到读取操作的重新开始的延迟降低。 可以电重写存储的信息的非易失性存储器在阱区中具有多个非易失性存储单元晶体管，其具有分别耦合到位线和源极线的漏电极和源电极以及耦合到字线的栅电极，并且基于阈值电压之间的差存储信息 读操作中的字线选择电平，而非易失性存储器具有低功耗模式。 在低功耗模式中，将低于电路接地电压并高于读操作所需的第一负电压的第二电压提供给阱区和字线。 当升压形成重写负电压时，负电压的电路节点不是低功耗模式下的电路接地电压。

公开(公告)号：US20050219935A1

公开(公告)日：2005-10-06

申请号：US11133232

申请日：2005-05-20

Applicant: Takao Watanabe ,  Ryoichi Hori ,  Goro Kitsukawa ,  Yoshiki Kawajiri ,  Takayuki Kawahara ,  Kiyoo Itoh

Inventor： Takao Watanabe ,  Ryoichi Hori ,  Goro Kitsukawa ,  Yoshiki Kawajiri ,  Takayuki Kawahara ,  Kiyoo Itoh

IPC: G11C5/14 ,  G11C7/00 ,  G11C7/12 ,  G11C8/00 ,  G11C8/10 ,  G11C11/4094 ,  H03K5/08 ,  H03K17/00 ,  H03K17/693 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/0944

CPC classification number: G11C7/12 ,  G11C5/14 ,  G11C5/147 ,  G11C8/10 ,  G11C11/4094 ,  G11C11/413 ,  H03K5/08 ,  H03K17/693 ,  H03K19/00376 ,  H03K19/00384 ,  H03K19/017 ,  H03K19/01707 ,  H03K19/017518 ,  H03K19/09448 ,  H03K2217/0036

Abstract: A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.

公开(公告)号：US06912172B2

公开(公告)日：2005-06-28

申请号：US10718562

申请日：2003-11-24

Applicant: Kazuki Honma ,  Yoshiki Kawajiri ,  Masashi Wada ,  Mikio Sugawara ,  Hirofumi Sonoyama

Inventor： Kazuki Honma ,  Yoshiki Kawajiri ,  Masashi Wada ,  Mikio Sugawara ,  Hirofumi Sonoyama

IPC: G01R31/28 ,  G11C5/14 ,  G11C16/02 ,  G11C16/16 ,  G11C16/30 ,  G11C17/00 ,  G11C29/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/44 ,  G11C8/00

CPC classification number: G11C29/028 ,  G11C5/14 ,  G11C16/04 ,  G11C16/30 ,  G11C29/006 ,  G11C29/02 ,  G11C29/12005 ,  G11C2029/5004

Abstract: Disclosed are a semiconductor chip which is uniquely value-added, a semiconductor integrated circuit device which improves the productivity and yield of products and facilitates the production management, and a method of manufacturing of semiconductor integrated circuit devices which enables the improvement of productivity and yield of products and the rational demand-responsive production management. The semiconductor chip includes a common circuit block which is operative at a first voltage and a second voltage that is higher than the first voltage, a first circuit block which is designed to fit the first voltage and operate in unison with the common circuit block, a second circuit block which is designed to fit the second voltage and operate in unison with the common circuit block, and a voltage type setup circuit which activates one of the first and second circuit blocks, with a first identification record indicative of the operability at the first voltage or a second identification record indicative of the operability only at the second voltage being held by the chip.

Abstract translation: 公开了一种独特增值的半导体芯片，提高产品的生产率和产量并促进生产管理的半导体集成电路器件，以及制造半导体集成电路器件的方法，其能够提高生产率和产量 产品和理性需求响应生产管理。 半导体芯片包括在第一电压和第二电压下操作的公共电路块，第二电压高于第一电压，被设计为适合第一电压并与公共电路块一致操作的第一电路块， 第二电路块，其被设计成适合第二电压并且与公共电路块一致地操作;以及电压类型建立电路，其激活第一和第二电路块中的一个，电压类型建立电路具有第一识别记录，其指示第一电压块的可操作性 电压或第二识别记录，仅指示在芯片所保持的第二电压下的可操作性。

公开(公告)号：US06567313B2

公开(公告)日：2003-05-20

申请号：US09964394

申请日：2001-09-28

Applicant: Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takashi Yamaki ,  Kiichi Makuta ,  Masashi Wada ,  Yoshiki Kawajiri

Inventor： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takashi Yamaki ,  Kiichi Makuta ,  Masashi Wada ,  Yoshiki Kawajiri

IPC: G11C700

CPC classification number: G11C16/3459 ,  G11C16/12 ,  G11C2216/14

Abstract: Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.

公开(公告)号：US06512398B1

公开(公告)日：2003-01-28

申请号：US09572443

申请日：2000-05-17

Applicant: Hirofumi Sonoyama ,  Yoshiki Kawajiri ,  Masashi Wada ,  Jun Eto ,  Shinji Kawai

Inventor： Hirofumi Sonoyama ,  Yoshiki Kawajiri ,  Masashi Wada ,  Jun Eto ,  Shinji Kawai

IPC: G01R1900

CPC classification number: G11C5/143 ,  G01R19/16552 ,  G05F3/242 ,  G11C16/30

Abstract: The reliability of a semiconductor integrated circuit device is remarkably improved by minimizing the fluctuations of the detection level of the supply voltage due to the manufacturing process and/or other factors. In the semiconductor integrated circuit device according to the invention, a differential amplifier circuit SA amplifies the differential voltage representing the difference between the reference voltage VREF generated by a reference voltage generating section 16 and the detection voltage obtained by dividing a supply voltage VCC by means of resistors 27 and 28 and outputs it as a detection signal K. The reference voltage generating section 16 generates reference voltage VREF from the base-emitter voltage of a bipolar transistor that is minimally affected by temperature and the manufacturing process so that the fluctuations of the detection level of the supply voltage VCC can be minimized.

Abstract translation: 通过最小化由于制造过程和/或其他因素导致的电源电压的检测水平的波动，可以显着提高半导体集成电路器件的可靠性。 在根据本发明的半导体集成电路器件中，差分放大器电路SA放大表示由参考电压产生部分16产生的参考电压VREF与由电源电压VCC分压所获得的检测电压之间的差异的差分电压， 电阻器27和28并将其输出作为检测信号K.参考电压产生部分16从由温度和制造过程影响最小的双极晶体管的基极 - 发射极电压产生参考电压VREF，使得检测的波动 电源电压VCC的电平可以最小化。

公开(公告)号：US06205556B1

公开(公告)日：2001-03-20

申请号：US09198658

申请日：1998-11-24

Applicant: Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

Inventor： Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

IPC: G06F126

CPC classification number: G06N3/063

Abstract: Herein disclosed is a data processing system having a memory packaged therein for realizing a large-scale and high-speed parallel distributed processing and, especially, a data processing system for the neural network processing. The neural network processing system according to the present invention comprises: a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; an input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operations of said memory circuit, said input/output circuit and said processing circuit. The processing circuit is constructed to include at least one of an adder, a multiplier, a nonlinear transfer function circuit and a comparator so that at least a portion of the processing necessary for determining the neutron output values such as the product or sum may be accomplished in parallel. Moreover, these circuits are shared among a plurality of neutrons and are operated in a time sharing manner to determine the plural neuron output values. Still moreover, the aforementioned comparator compares the neuron output value determined and the desired value of the output in parallel.

Abstract translation: 这里公开了一种数据处理系统，其中封装有用于实现大规模和高速并行分布式处理的存储器，特别是用于神经网络处理的数据处理系统。 根据本发明的神经网络处理系统包括：存储电路，用于存储神经元输出值，连接权重，输出的期望值和学习所需的数据; 用于将数据写入或读出所述存储电路的输入/输出电路; 用于执行用于确定诸如存储在所述存储器电路中的数据的乘积，和和非线性转换的神经元输出，输出值与其期望值的比较以及学习所需的处理的处理的处理电路; 以及用于控制所述存储电路，所述输入/输出电路和所述处理电路的操作的控制电路。 处理电路被构造为包括加法器，乘法器，非线性传递函数电路和比较器中的至少一个，使得可以实现用于确定诸如乘积或和的中子输出值所需的处理的至少一部分 在平行下。 此外，这些电路在多个中子之间共享并且以分时方式操作以确定多个神经元输出值。 此外，上述比较器并行地比较所确定的神经元输出值和输出的期望值。

公开(公告)号：US5118633A

公开(公告)日：1992-06-02

申请号：US557649

申请日：1990-07-25

Applicant: Kazuhiko Sagara ,  Kiyoo Itoh ,  Goro Kitsukawa ,  Yoshifumi Kawamoto ,  Yoshiki Kawajiri

Inventor： Kazuhiko Sagara ,  Kiyoo Itoh ,  Goro Kitsukawa ,  Yoshifumi Kawamoto ,  Yoshiki Kawajiri

IPC: H01L21/8242 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/10 ,  H01L27/108

CPC classification number: H01L21/8249 ,  H01L27/0623 ,  H01L27/10817 ,  Y10S148/144

Abstract: Sources and drains of MOS transistors are formed after the formation of an emitter of a bipolar transistor, whereby the sources and drains are made smaller in thickness than the emitter. Since the sources and drains are not subjected to a high-temperature heat treatment conducted in the formation of the emitter, there is no fear of increase in thickness of the sources and drains caused by the diffusion of impurities. There can be formed a BiCMOS having a high integration density and superior characteristics.

公开(公告)号：US4316265A

公开(公告)日：1982-02-16

申请号：US94927

申请日：1979-11-16

Applicant: Hirotoshi Tanaka ,  Yoshiki Kawajiri ,  Kouetsu Chiba ,  Ryoichi Hori ,  Kiyoo Itoh

Inventor： Hirotoshi Tanaka ,  Yoshiki Kawajiri ,  Kouetsu Chiba ,  Ryoichi Hori ,  Kiyoo Itoh

IPC: G11C11/413 ,  G11C8/00 ,  G11C11/408 ,  G11C11/40

CPC classification number: G11C11/4087 ,  G11C8/00

Abstract: In a memory device, row and column decoders are connected through a common address signal line to an address buffer, and the row decoder is connected through a switch to the common address signal line. When the address buffer delivers a first address signal, the switch is turned on so that the first address signal is applied to both of the column and row decoders. The column decoder includes therein provision for disabling the column decoder when the first address signal is applied to column decoder. The column decoder therefore does not respond to the first address signal. Subsequently, when the address buffer delivers a second address signal, the switch is turned off so that the row decoder is not applied with the second address signal but the column decoder responds to the second address signal. Thus, the row and column address respond to the first and second address signals respectively.

Abstract translation: 在存储器件中，行和列解码器通过公共地址信号线连接到地址缓冲器，并且行解码器通过开关连接到公共地址信号线。 当地址缓冲器传送第一个地址信号时，开关导通，使得第一个地址信号被应用于列和行解码器。 列解码器包括其中当第一地址信号被应用于列解码器时禁用列解码器的设置。 因此，列解码器不响应于第一地址信号。 随后，当地址缓冲器传送第二地址信号时，开关被关断，使得行解码器不被施加第二地址信号，但是列译码器响应于第二地址信号。 因此，行和列地址分别响应于第一和第二地址信号。