公开(公告)号：US20180102251A1

公开(公告)日：2018-04-12

申请号：US15725030

申请日：2017-10-04

Applicant: Invensas Bonding Technologies, Inc.

Inventor： Javier A. DELACRUZ ,  Steven L. TEIG ,  Shaowu HUANG ,  William C. PLANTS ,  David Edward FISCH

IPC: H01L21/20 ,  H01L21/48 ,  H01L21/74 ,  H01L21/82

Abstract: Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates. The architecture facilitates ASIC, ASSP, and FPGA ICs and neural networks, reducing footprint and power requirements.

公开(公告)号：US11760059B2

公开(公告)日：2023-09-19

申请号：US16521493

申请日：2019-07-24

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Qin-Yi Tong

IPC: B32B7/04 ,  B81C1/00 ,  H01L21/3105 ,  H01L21/762 ,  H01L23/00

CPC classification number: B32B7/04 ,  B81C1/00357 ,  H01L21/3105 ,  H01L21/76251 ,  H01L24/26 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  B32B2250/04 ,  B81C2201/019 ,  B81C2203/019 ,  B81C2203/0118 ,  H01L2224/0401 ,  H01L2224/08059 ,  H01L2224/29186 ,  H01L2224/80896 ,  H01L2224/81894 ,  H01L2224/81895 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/92125 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01058 ,  H01L2924/01067 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/351 ,  Y10T156/10 ,  Y10T428/24355 ,  Y10T428/24942 ,  Y10T428/31504 ,  Y10T428/31678 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2224/29186 ,  H01L2924/05442 ,  H01L2224/9212 ,  H01L2224/81895 ,  H01L2224/80896 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/1305 ,  H01L2924/00 ,  H01L2924/351 ,  H01L2924/00

Abstract: A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH2 species. This may be accomplished by exposing the bonding layer to an NH4OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.

公开(公告)号：US20220319901A1

公开(公告)日：2022-10-06

申请号：US17708688

申请日：2022-03-30

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Dominik Suwito ,  Gaius Gillman Fountain, JR. ,  Guilian Gao

IPC: H01L21/683 ,  H01L21/78

Abstract: A bonding method is disclosed. The method can include directly bonding a first nonconductive bonding material of a semiconductor element to a second nonconductive bonding material of a carrier without an intervening adhesive. The first nonconductive bonding material is disposed on a device portion of the semiconductor element. The second nonconductive bonding material is disposed on a bulk portion of the carrier. A deposited dielectric layer is disposed between the device portion and the bulk portion. The method can include removing the carrier from the semiconductor element by transferring thermal energy to the dielectric layer to induce diffusion of gas out of the dielectric layer.

公开(公告)号：US20220302058A1

公开(公告)日：2022-09-22

申请号：US17836840

申请日：2022-06-09

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Guilian Gao ,  Bongsub Lee ,  Gaius Gillman Fountain, Jr. ,  Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi ,  Belgacem Haba ,  Rajesh Katkar

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48

Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.

公开(公告)号：US20220285303A1

公开(公告)日：2022-09-08

申请号：US17684841

申请日：2022-03-02

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Laura Wills Mirkarimi ,  Cyprian Emeka Uzoh

IPC: H01L23/00

Abstract: A bonded structure is disclosed. The bonded structure can include a first element that includes a first conductive feature and a first nonconductive region. The first conductive feature can include a fine grain metal that has an average grain size of 500 nm or less. The bonded structure can include a second element that includes a second conductive feature and a second nonconductive region. The first conductive feature is directly bonded to the second conductive feature without an intervening adhesive, and the second nonconductive region is directly bonded to the second nonconductive region without an intervening adhesive.

公开(公告)号：US20220285236A1

公开(公告)日：2022-09-08

申请号：US17825240

申请日：2022-05-26

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Guilian Gao ,  Laura Wills Mirkarimi ,  Gaius Gillman Fountain, Jr.

IPC: H01L21/66 ,  H01L21/768 ,  H01L23/532 ,  H01L23/538 ,  H01L23/522

Abstract: Mitigating surface damage of probe pads in preparation for direct bonding of a substrate is provided. Methods and layer structures prepare a semiconductor substrate for direct bonding processes by restoring a flat direct-bonding surface after disruption of probe pad surfaces during test probing. An example method fills a sequence of metals and oxides over the disrupted probe pad surfaces and builds out a dielectric surface and interconnects for hybrid bonding. The interconnects may be connected to the probe pads, and/or to other electrical contacts of the substrate. A layer structure is described for increasing the yield and reliability of the resulting direct bonding process. Another example process builds the probe pads on a next-to-last metallization layer and then applies a direct bonding dielectric layer and damascene process without increasing the count of mask layers. Another example process and related layer structure recesses the probe pads to a lower metallization layer and allows recess cavities over the probe pads.

公开(公告)号：US11417576B2

公开(公告)日：2022-08-16

申请号：US16678058

申请日：2019-11-08

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Rajesh Katkar ,  Liang Wang ,  Cyprian Emeka Uzoh ,  Shaowu Huang ,  Guilian Gao ,  Ilyas Mohammed

IPC: H01L23/10 ,  B81C1/00 ,  B81B7/00 ,  H01L23/04 ,  H01L23/053 ,  H01L23/02

Abstract: Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.

公开(公告)号：US20220254746A1

公开(公告)日：2022-08-11

申请号：US17677161

申请日：2022-02-22

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Paul M. Enquist

IPC: H01L23/00 ,  H01L21/50 ,  H01L25/065 ,  H01L25/00

Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

公开(公告)号：US20220208702A1

公开(公告)日：2022-06-30

申请号：US17564550

申请日：2021-12-29

Applicant: Invensas Bonding Technologies, Inc.

Inventor： Cyprian Emeka Uzoh

IPC: H01L23/00

Abstract: An element is disclosed. The element can include a non-conductive structure having a non-conductive bonding surface, a cavity at least partially extending through a portion of a thickness of the non-conductive structure from the non-conductive bonding surface, and a conductive pad disposed in the cavity. The cavity has a bottom side and a sidewall. The conductive pad has a bonding surface and a back side opposite the bonding surface. An average size of the grains at the bonding surface is smaller than an average size of the grains adjacent the bottom side of the cavity. The conductive pad can include a crystal structure with grains oriented along a 111 crystal plane. The element can be bonded to another element to form a bonded structure. The element and the other element can be directly bonded to one another without an intervening adhesive.

公开(公告)号：US20220208650A1

公开(公告)日：2022-06-30

申请号：US17562967

申请日：2021-12-27

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Guilian Gao ,  Gaius Gillman Fountain, JR.

IPC: H01L23/48 ,  H01L21/768

Abstract: A microelectronic structure is disclosed. The microelectronic structure can include a bulk semiconductor portion that has a first surface and a second surface opposite the first surface. The microelectronic structure can include a via structure that extends at least partially through the bulk semiconductor portion along a direction non-parallel to the first surface. The microelectronic structure can include a first dielectric barrier layer that is disposed on the first surface of the bulk semiconductor portion and extends to the via structure. The microelectronic structure can include a second dielectric layer that is disposed on the first dielectric barrier layer and extends to the via structure.