-
公开(公告)号：US20180102251A1
公开(公告)日：2018-04-12
申请号：US15725030
申请日：2017-10-04
摘要： Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates. The architecture facilitates ASIC, ASSP, and FPGA ICs and neural networks, reducing footprint and power requirements.
-
2.发明申请公开(公告)号：US20200075520A1
公开(公告)日：2020-03-05
申请号：US16553535
申请日：2019-08-28
发明人： Guilian GAO , Javier A. DELACRUZ , Shaowu HUANG , Liang WANG , Gaius Gillman FOUNTAIN, JR. , Rajesh KATKAR , Cyprian Emeka UZOH
IPC分类号： H01L23/00
摘要： Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process.
-
公开(公告)号：US20190181107A1
公开(公告)日：2019-06-13
申请号：US16189804
申请日：2018-11-13
发明人： Javier A. DELACRUZ , Rajesh KATKAR , Shaowu HUANG , Gaius Gillman FOUNTAIN, JR. , Liang WANG , Laura Wills MIRKARIMI
IPC分类号： H01L23/00 , H01L21/768 , H01L23/48 , H01L25/065
摘要： Representative implementations of techniques and devices are used to remedy or mitigate the effects of damaged interconnect pads of bonded substrates. A recess of predetermined size and shape is formed in the surface of a second substrate of the bonded substrates, at a location that is aligned with the damaged interconnect pad on the first substrate. The recess encloses the damage or surface variance of the pad, when the first and second substrates are bonded.
-
4.发明申请公开(公告)号：US20200075533A1
公开(公告)日：2020-03-05
申请号：US16553879
申请日：2019-08-28
发明人： Guilian GAO , Javier A. DELACRUZ , Shaowu HUANG , Liang WANG , Gaius Gillman FOUNTAIN, Jr. , Rajesh KATKAR , Cyprian Emeka UZOH
IPC分类号： H01L23/00
摘要： Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process.
-
5.发明申请公开(公告)号：US20190265411A1
公开(公告)日：2019-08-29
申请号：US16247262
申请日：2019-01-14
发明人： Shaowu HUANG , Javier A. DELACRUZ , Liang WANG , Guilian GAO
IPC分类号： G02B6/13
摘要： Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects are provided. An example optical interconnect joins first and second optical conduits. A first direct oxide bond at room temperature joins outer claddings of the two optical conduits and a second direct bond joins the inner light-transmitting cores of the two conduits at an annealing temperature. The two low-temperature bonds allow photonics to coexist in an integrated circuit or microelectronics package without conventional high-temperatures detrimental to microelectronics. Direct-bonded square, rectangular, polygonal, and noncircular optical interfaces provide better matching with rectangular waveguides and better performance. Direct oxide-bonding processes can be applied to create running waveguides, photonic wires, and optical routing in an integrated circuit package or in chip-to-chip optical communications without need for conventional optical couplers. An example wafer-level process fabricates running waveguides, optical routing, and direct-bonded optical interconnects for silicon photonics and optoelectronics packages when two wafers are joined.
-
公开(公告)号：US20180331000A1
公开(公告)日：2018-11-15
申请号：US15837941
申请日：2017-12-11
摘要： Representative implementations of devices and techniques provide a temporary access point (e.g., for testing, programming, etc.) for a targeted interconnect located among multiple finely spaced interconnects on a surface of a microelectronic component. One or more sacrificial layers are disposed on the surface of the microelectronic component, overlaying the multiple interconnects. An insulating layer is disposed between a conductive layer and the surface, and includes a conductive via through the insulating layer that electrically couples the conductive layer to the target interconnect. The sacrificial layers are configured to be removed after the target interconnect has been accessed, without damaging the surface of the microelectronic component.
-
公开(公告)号：US20210242152A1
公开(公告)日：2021-08-05
申请号：US17168034
申请日：2021-02-04
IPC分类号： H01L23/00
摘要： A bonded structure and a method of forming such a bonded structure are disclosed. The bonded structure can include a first element and a second element. The first element has a first bonding surface including a first nonconductive material and a plurality of first contact pads. The first contact pads are electrically connected to one or more first microelectronic devices in the first element. The second element has a second bonding surface including a second nonconductive material and a plurality of second contact pads. The second contact pads are electrically connected to one or more second microelectronic devices in the second element. The second bonding surface is directly bonded to the first bonding surface without an intervening adhesive to form a bonding interface, and one or more first contact pads is omitted from the first microelectronic element to alter the functionality of the bonded structure.
-
公开(公告)号：US20200105630A1
公开(公告)日：2020-04-02
申请号：US16701606
申请日：2019-12-03
摘要： Representative implementations of devices and techniques provide a temporary access point (e.g., for testing, programming, etc.) for a targeted interconnect located among multiple finely spaced interconnects on a surface of a microelectronic component. One or more sacrificial layers are disposed on the surface of the microelectronic component, overlaying the multiple interconnects. An insulating layer is disposed between a conductive layer and the surface, and includes a conductive via through the insulating layer that electrically couples the conductive layer to the target interconnect. The sacrificial layers are configured to be removed after the target interconnect has been accessed, without damaging the surface of the microelectronic component.
-
-
-
-
-
-
-
搜索结果
8 条记录 (耗时 0.015 秒)
