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    Probe methodology for ultrafine pitch Interconnects
    2.
    发明申请
    Probe methodology for ultrafine pitch Interconnects 审中-公开

    公开(公告)号：US20180331000A1

    公开(公告)日：2018-11-15

    申请号：US15837941

    申请日：2017-12-11

    申请人： Invensas Bonding Technologies, Inc.

    发明人： Javier A. DELACRUZ ,  Paul M. ENQUIST ,  Gaius Gillman FOUNTAIN, JR. ,  Ilyas MOHAMMED

    IPC分类号： H01L21/66 ,  H01L23/00

    摘要： Representative implementations of devices and techniques provide a temporary access point (e.g., for testing, programming, etc.) for a targeted interconnect located among multiple finely spaced interconnects on a surface of a microelectronic component. One or more sacrificial layers are disposed on the surface of the microelectronic component, overlaying the multiple interconnects. An insulating layer is disposed between a conductive layer and the surface, and includes a conductive via through the insulating layer that electrically couples the conductive layer to the target interconnect. The sacrificial layers are configured to be removed after the target interconnect has been accessed, without damaging the surface of the microelectronic component.

    PROBE METHODOLOGY FOR ULTRAFINE PITCH INTERCONNECTS
    3.
    发明申请
    PROBE METHODOLOGY FOR ULTRAFINE PITCH INTERCONNECTS 审中-公开

    公开(公告)号：US20200105630A1

    公开(公告)日：2020-04-02

    申请号：US16701606

    申请日：2019-12-03

    申请人： Invensas Bonding Technologies, Inc.

    发明人： Javier A. DELACRUZ ,  Paul M. ENQUIST ,  Gaius Gillman FOUNTAIN, JR. ,  Ilyas MOHAMMED

    IPC分类号： H01L21/66 ,  H01L23/00

    摘要： Representative implementations of devices and techniques provide a temporary access point (e.g., for testing, programming, etc.) for a targeted interconnect located among multiple finely spaced interconnects on a surface of a microelectronic component. One or more sacrificial layers are disposed on the surface of the microelectronic component, overlaying the multiple interconnects. An insulating layer is disposed between a conductive layer and the surface, and includes a conductive via through the insulating layer that electrically couples the conductive layer to the target interconnect. The sacrificial layers are configured to be removed after the target interconnect has been accessed, without damaging the surface of the microelectronic component.