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    Semiconductor device manufacturing method using oxygen diffusion barrier layer between buried oxide layer and high K dielectric layer
    61.
    发明授权
    Semiconductor device manufacturing method using oxygen diffusion barrier layer between buried oxide layer and high K dielectric layer 有权
    在掩埋氧化层和高K电介质层之间使用氧扩散阻挡层的半导体器件制造方法

    公开(公告)号：US07833891B2

    公开(公告)日：2010-11-16

    申请号：US12178303

    申请日：2008-07-23

    申请人： Kagguo Cheng ,  Bruce B. Doris

    发明人： Kagguo Cheng ,  Bruce B. Doris

    IPC分类号： H01L21/28 ,  H01L29/423

    CPC分类号： H01L29/66795 ,  H01L29/785

    摘要： A semiconductor device and method is provided that has an oxygen diffusion barrier layer between a high-k dielectric and BOX. The method includes depositing a diffusion barrier layer on a BOX layer and gate structure and etching a portion of the diffusion barrier layer from sidewalls of the gate structure. The method further includes depositing a high-k dielectric on the diffusion barrier layer and the gate structure.

    摘要翻译： 提供了在高k电介质和BOX之间具有氧扩散阻挡层的半导体器件和方法。 该方法包括在BOX层和栅极结构上沉积扩散阻挡层，并从栅极结构的侧壁蚀刻扩散阻挡层的一部分。 该方法还包括在扩散阻挡层和栅极结构上沉积高k电介质。

    Gate patterning scheme with self aligned independent gate etch
    63.
    发明授权
    Gate patterning scheme with self aligned independent gate etch 失效
    具有自对准独立栅极蚀刻的栅极图案化方案

    公开(公告)号：US07749903B2

    公开(公告)日：2010-07-06

    申请号：US12027444

    申请日：2008-02-07

    申请人： Scott D. Halle ,  Matthew E. Colburn ,  Bruce B. Doris ,  Thomas W. Dyer

    发明人： Scott D. Halle ,  Matthew E. Colburn ,  Bruce B. Doris ,  Thomas W. Dyer

    IPC分类号： H01L21/44

    CPC分类号： H01L21/32139 ,  H01L21/266 ,  H01L21/28123 ,  H01L21/823828

    摘要： A method for self-aligned gate patterning is disclosed. Two masks are used to process adjacent semiconductor components, such as an nFET and pFET that are separated by a shallow trench isolation region. The mask materials are chosen to facilitate selective etching. The second mask is applied while the first mask is still present, thereby causing the second mask to self align to the first mask. This avoids the undesirable formation of a stringer over the shallow trench isolation region, thereby improving the yield of a semiconductor manufacturing operation.

    摘要翻译： 公开了一种用于自对准栅极图案化的方法。 使用两个掩模来处理相邻的半导体部件，例如由浅沟槽隔离区分隔的nFET和pFET。 选择掩模材料以便于选择性蚀刻。 当第一掩模仍然存在时，施加第二掩模，从而使第二掩模与第一掩模自对准。 这避免了在浅沟槽隔离区域上不期望地形成纵梁，从而提高半导体制造操作的产量。

    Methods of forming mixed gate CMOS with single poly deposition
    64.
    发明授权
    Methods of forming mixed gate CMOS with single poly deposition 有权
    使用单个聚合物沉积形成混合栅极CMOS的方法

    公开(公告)号：US07741181B2

    公开(公告)日：2010-06-22

    申请号：US11936061

    申请日：2007-11-06

    申请人： Bruce B. Doris ,  Charlotte DeWan Adams ,  Naim Moumen ,  Ying Zhang

    发明人： Bruce B. Doris ,  Charlotte DeWan Adams ,  Naim Moumen ,  Ying Zhang

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/785

    摘要： A method for fabricating metal gate and polysilicon gate FET devices on the same chip is disclosed. The method avoids the use of two separate masks during gate stack fabrication of the differing gates. By using a single mask, tighter NFET to PFET distances can be achieved, and the fabrication process is simplified. After blanket disposing layers for the fabrication of the metal gate stack, a covering protective material layer is formed, again in blanket fashion. A block level mask is used to clear the surface for the gate insulator formation in the poly gate device regions. During oxidation, which forms the gate dielectric for the poly gate devices, the protective material prevents damage of the metal gate device regions. Following oxidation, a single common polysilicon cover is disposed in blanket manner for continuing the fabrication of the gate stacks. The protective material is selected in such a way to be either easily removable upon oxidation, or to be conductive upon oxidation. In this latter case the oxidized protective material is incorporated into the metal gate stack, which incorporation results in a novel CMOS structure.

    摘要翻译： 公开了一种在同一芯片上制造金属栅极和多晶硅栅极FET器件的方法。 该方法避免了在不同栅极的栅堆叠制造期间使用两个分离的掩模。 通过使用单个掩模，可以实现更紧密的NFET至PFET距离，并简化制造工艺。 在用于制造金属栅极堆叠的毯布设置层之后，再次以毯子形式形成覆盖保护材料层。 块级别掩模用于清除多晶硅栅极器件区域中的栅极绝缘体形成的表面。 在形成用于多晶硅栅极器件的栅极电介质的氧化期间，保护材料防止金属栅极器件区域的损坏。 在氧化之后，以橡皮布方式设置单个公共多晶硅盖，以继续制造栅极堆叠。 保护材料选择为在氧化时易于除去或在氧化时导电。 在后一种情况下，氧化的保护材料被并入到金属栅极堆叠中，其结合形成了新的CMOS结构。

    Reduction of boron diffusivity in pFETs
    65.
    发明授权
    Reduction of boron diffusivity in pFETs 失效
    降低pFET中的硼扩散率

    公开(公告)号：US07737014B2

    公开(公告)日：2010-06-15

    申请号：US10596249

    申请日：2003-12-08

    申请人： Frederick William Buehrer ,  Dureseti Chidambarrao ,  Bruce B. Doris ,  Hsiang-Jen Huang ,  Haining Yang

    发明人： Frederick William Buehrer ,  Dureseti Chidambarrao ,  Bruce B. Doris ,  Hsiang-Jen Huang ,  Haining Yang

    IPC分类号： H01L21/22 ,  H01L21/38

    CPC分类号： H01L29/7842 ,  H01L21/22 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

    摘要： A stressed film applied across a boundary defined by a structure or a body (e.g. substrate or layer) of semiconductor material provides a change from tensile to compressive stress in the semiconductor material proximate to the boundary and is used to modify boron diffusion rate during annealing and thus modify final boron concentrations. In the case of a field effect transistor, the gate structure may be formed with or without sidewalls to regulate the location of the boundary relative to source/drain, extension and/or halo implants. Different boron diffusion rates can be produced in the lateral and vertical directions and diffusion rates comparable to arsenic can be achieved. Reduction of junction capacitance of both nFETs and pFETs can be achieved simultaneously with the same process steps.

    摘要翻译： 应用于由半导体材料的结构或主体（例如衬底或层）限定的边界处的应力膜提供了靠近边界的半导体材料中的拉应力和压缩应力的变化，并用于在退火过程中修饰硼扩散速率， 从而改变最终的硼浓度。 在场效应晶体管的情况下，栅极结构可以形成有或不具有侧壁以调节边界相对于源极/漏极，延伸和/或晕轮植入物的位置。 可以在横向和垂直方向上产生不同的硼扩散速率，并且可以实现与砷相当的扩散速率。 可以通过相同的工艺步骤同时实现nFET和pFET的结电容的减小。

    Mobility enhanced CMOS devices
    68.
    发明授权
    Mobility enhanced CMOS devices 有权
    移动增强CMOS器件

    公开(公告)号：US07569848B2

    公开(公告)日：2009-08-04

    申请号：US11362773

    申请日：2006-02-28

    申请人： Michael P. Belyansky ,  Bruce B. Doris ,  Oleg G. Gluschenkov

    发明人： Michael P. Belyansky ,  Bruce B. Doris ,  Oleg G. Gluschenkov

    IPC分类号： H01L29/06

    CPC分类号： H01L29/0653 ,  H01L29/66636 ,  H01L29/7848

    摘要： Compressive or tensile materials are selectively introduced beneath and in alignment with spacer areas and adjacent to channel areas of a semiconductor substrate to enhance or degrade electron and hole mobility in CMOS circuits. A process entails steps of creating dummy spacers, forming a dielectric mandrel (i.e., mask), removing the dummy spacers, etching recesses into the underlying semiconductor substrate, introducing a compressive or tensile material into a portion of each recess, and filling the remainder of each recess with substrate material.

    摘要翻译： 压缩或拉伸材料被选择性地引入到间隔区域的下方并且与半导体衬底的通道区域相邻并且与CMOS电路中的电子和空穴迁移率相关联。 一个过程需要创建虚拟间隔物的步骤，形成介质心轴（即掩模），去除虚拟间隔物，将凹槽蚀刻到下面的半导体衬底中，将压缩或拉伸材料引入每个凹部的一部分中， 每个凹槽与基底材料。

    ANISOTROPIC STRESS GENERATION BY STRESS-GENERATING LINERS HAVING A SUBLITHOGRAPHIC WIDTH
    69.
    发明申请
    ANISOTROPIC STRESS GENERATION BY STRESS-GENERATING LINERS HAVING A SUBLITHOGRAPHIC WIDTH 失效
    通过应力产生具有子平面宽度的衬垫的各向异性应力生成

    公开(公告)号：US20090184374A1

    公开(公告)日：2009-07-23

    申请号：US12017557

    申请日：2008-01-22

    申请人： Lawrence A. Clevenger ,  Bruce B. Doris ,  Elbert E. Huang ,  Sampath Purushothaman ,  Carl J. Radens

    发明人： Lawrence A. Clevenger ,  Bruce B. Doris ,  Elbert E. Huang ,  Sampath Purushothaman ,  Carl J. Radens

    IPC分类号： H01L21/336 ,  H01L29/78

    CPC分类号： H01L21/31144 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843

    摘要： A protruding structure having a linear edge is formed on a substrate. The protruding structure may be a gate line of a field effect transistor. A stress-generating liner is deposited on the substrate. A non-photosensitive self-assembling block copolymer layer containing at least two immiscible polymeric block components is deposited on the stress-generating liner, and is annealed to allow phase separation of immiscible components. The polymeric resist is developed to remove at least one of the at least two polymeric block components, which formed a pattern of nested lines due to the linear edge of the protruding structure. Linear nanoscale stripes are formed in the polymeric resist which is self-aligning and self-assembled. The stress-generating layer is patterned into linear stress-generating stripes having a sublithographic width. The linear stress-generating stripes provide a predominantly uniaxial stress along their lengthwise direction, providing an anisotropic stress to an underlying semiconductor device.

    摘要翻译： 在基板上形成具有线性边缘的突出结构。 突出结构可以是场效应晶体管的栅极线。 应力产生衬垫沉积在衬底上。 含有至少两种不混溶的聚合物嵌段组分的非感光性自组装嵌段共聚物层沉积在应力产生衬里上，并进行退火以允许不相容的组分相分离。 聚合物抗蚀剂被显影以除去至少两个聚合物嵌段组分中的至少一个，其由于突出结构的线性边缘而形成嵌套线的图案。 在自对准和自组装的聚合物抗蚀剂中形成线性纳米级条纹。 将应力产生层图案化成具有亚光刻宽度的线性应力产生条纹。 线性应力产生条纹沿其长度方向提供主要的单轴应力，向下面的半导体器件提供各向异性的应力。