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    Communication system and method
    52.
    发明授权
    Communication system and method 有权
    通信系统及方法

    公开(公告)号：US09490967B1

    公开(公告)日：2016-11-08

    申请号：US14978363

    申请日：2015-12-22

    Applicant: Texas Instruments Incorporated

    Inventor： Robert Floyd Payne

    IPC: H04L5/20 ,  H04L7/027 ,  H04L25/02 ,  H04L1/00 ,  H04L7/00 ,  H04L25/14

    CPC classification number: H04L25/0272 ,  G06F13/38 ,  H04L1/0045 ,  H04L7/0008 ,  H04L7/0066 ,  H04L25/4917

    Abstract: A communication system includes a receiver for decoding data having three states of −1, 0, and 1. The receiver includes a first input coupled to a first data line, a second input coupled to a second data line, and a third input coupled to a third data line. A first comparator is coupled to a first output, wherein the first comparator is for generating data signals in response to the sign of voltages on the first data line minus voltages on the second data line. A second comparator is coupled to a second output, wherein the second comparator is for generating clock signals in response to the sign of voltages on the third data line minus the average of voltages on the first and second data lines.

    Abstract translation: 通信系统包括用于解码具有三个状态-1,0和1的数据的接收器。接收机包括耦合到第一数据线的第一输入，耦合到第二数据线的第二输入和耦合到第二数据线的第三输入 第三条数据线。 第一比较器耦合到第一输出，其中第一比较器用于响应于第一数据线上的电压的符号减去第二数据线上的电压来产生数据信号。 第二比较器耦合到第二输出，其中第二比较器用于响应于第三数据线上的电压的符号减去第一和第二数据线上的电压的平均来产生时钟信号。

    Symbol transition clocking clock and data recovery to suppress excess clock caused by symbol glitch during stable symbol period
    53.
    发明授权
    Symbol transition clocking clock and data recovery to suppress excess clock caused by symbol glitch during stable symbol period 有权
    符号转换时钟时钟和数据恢复，以在稳定的符号周期期间抑制由符号毛刺引起的多余时钟

    公开(公告)号：US09490964B2

    公开(公告)日：2016-11-08

    申请号：US14555097

    申请日：2014-11-26

    Applicant: QUALCOMM Incorporated

    Inventor： Shoichiro Sengoku

    IPC: H04L27/10 ,  H03D13/00 ,  H04L7/00 ,  H04L7/04 ,  H04L7/08 ,  G11C8/06 ,  G06F13/40 ,  H04L7/033 ,  H04L25/14 ,  H04L25/49

    CPC classification number: H04L7/0087 ,  G06F13/4072 ,  G11C8/06 ,  H04L7/0037 ,  H04L7/0083 ,  H04L7/033 ,  H04L7/042 ,  H04L7/08 ,  H04L25/14 ,  H04L25/49

    Abstract: A method and an apparatus are provided. The apparatus may includes a clock recovery circuit having a comparator that provides a comparison signal indicating whether an input signal matches a level-latched instance of the input signal, a first set-reset latch that provides a filtered version of the comparison signal, where the first set-reset latch is set by a first-occurring active transition of the comparison signal and is unaffected by further transitions of the comparison signal that occur during a predefined period of time, delay circuitry that receives the filtered version of the comparison signal and outputs a first pulse on a first clock signal, and a second set-reset latch configured to provide a second pulse on an output clock signal when the first pulse is present on the first clock signal and the comparison signal indicates that the level-latched instance of the input signal does not match the input signal.

    Abstract translation: 提供了一种方法和装置。 该装置可以包括具有比较器的时钟恢复电路，该比较器提供指示输入信号是否匹配输入信号的电平锁存实例的比较信号，提供比较信号的滤波版本的第一设置复位锁存器，其中 第一设置复位锁存器由比较信号的第一次有效转换设置，并且不受在预定时间段期间发生的比较信号的进一步转换的影响，接收比较信号的滤波版本的延迟电路和输出 第一时钟信号上的第一脉冲和第二设置复位锁存器，其被配置为当第一时钟信号上存在第一脉冲时，在输出时钟信号上提供第二脉冲，并且比较信号指示电平锁存的实例 输入信号与输入信号不匹配。

    WIRELESS DEVICE AND DATA TRANSFER METHOD
    54.
    发明申请
    WIRELESS DEVICE AND DATA TRANSFER METHOD 审中-公开
    无线设备和数据传输方法

    公开(公告)号：US20160323126A1

    公开(公告)日：2016-11-03

    申请号：US15081920

    申请日：2016-03-27

    Applicant: FUJITSU LIMITED

    Inventor： Noboru MASUDA ,  Junya MORITA ,  Kenji IWAI

    IPC: H04L25/14 ,  H04W88/08 ,  H04L25/02

    CPC classification number: H04W88/08 ,  H04L5/001 ,  H04L5/0064 ,  H04L5/0066 ,  H04L5/0085 ,  H04L5/0091 ,  H04L25/0262 ,  H04L25/14 ,  H04W76/15 ,  Y02D70/00

    Abstract: A wireless device includes a processor that includes a first interface for transmitting and receiving data, a second interface that transfers data to and from the first interface, and a memory connected to the processor. The processor executes a process including acquiring carrier bandwidth information on baseband data used for wireless communication, calculating a needed data rate for transferring the baseband data between the first interface and the second interface, based on the acquired carrier bandwidth information, determining number of transfer paths for simultaneously transferring the baseband data between the first interface and the second interface, based on the calculated needed data rate, and causing the first interface and the second interface to transmit and receive the baseband data by simultaneously using the determined number of transfer paths.

    Abstract translation: 无线设备包括处理器，其包括用于发送和接收数据的第一接口，向第一接口传送数据和从第一接口传送数据的第二接口以及连接到处理器的存储器。 处理器执行包括获取用于无线通信的基带数据的载波带宽信息的处理，基于获取的载波带宽信息，确定传送路径的数量来计算用于在第一接口和第二接口之间传送基带数据的所需数据速率 用于基于所计算的所需数据速率在第一接口和第二接口之间同时传送基带数据，并且使第一接口和第二接口通过同时使用确定的传送路径数来发送和接收基带数据。

    Data transmission coordination over digital subscriber lines
    55.
    发明授权
    Data transmission coordination over digital subscriber lines 有权

    公开(公告)号：US09485025B2

    公开(公告)日：2016-11-01

    申请号：US14923604

    申请日：2015-10-27

    Applicant: Futurewei Technologies, Inc.

    Inventor： Yuanqiu Luo ,  Frank Effenberger

    IPC: H04J14/08 ,  H04B10/27 ,  H04B3/32 ,  H04L25/08 ,  H04L25/14 ,  H04J3/10 ,  H04J3/16 ,  H04L12/64

    CPC classification number: H04B10/27 ,  H04B3/32 ,  H04J3/10 ,  H04J3/1694 ,  H04L25/085 ,  H04L25/14 ,  H04L2012/6478

    Abstract: An optical management node comprising a memory comprising instructions, a processor coupled to the memory and configured execute the instructions, wherein executing the instructions causes the processor to schedule data transmissions across an electrical network between a plurality of user terminals and an optoelectrical interface by using time division multiplexing or time division multiple access based on optimization of crosstalk performance of electrical lines of the electrical network, and a transmitter coupled to the processor and configured to transmit schedule information to the optoelectrical interface via an optical network. Also disclosed is a method implemented in a management node comprising scheduling data transmissions with a plurality of user terminals across a Digital Subscriber Line (DSL) network using time division scheduling based on optimization of crosstalk performance of DSL lines of the DSL network, and transmitting schedule information to the user terminals via an optical network.

    Optical transceiver and method with channel binding, clock forwarding, and integrate-and-dump receivers
    60.
    发明授权
    Optical transceiver and method with channel binding, clock forwarding, and integrate-and-dump receivers 有权
    具有通道绑定，时钟转发和集成转储接收器的光收发器和方法

    公开(公告)号：US09413520B2

    公开(公告)日：2016-08-09

    申请号：US14104534

    申请日：2013-12-12

    Applicant: Vladimir Pelekhaty ,  Michael Y. Frankel

    Inventor： Vladimir Pelekhaty ,  Michael Y. Frankel

    IPC: H04J14/02 ,  H04B10/40 ,  H04J7/00 ,  H04L25/14 ,  H04L7/00

    CPC classification number: H04L7/0075 ,  H04B10/40 ,  H04J7/00 ,  H04J14/02 ,  H04J14/0226 ,  H04L7/0008 ,  H04L25/14

    Abstract: An optical transceiver includes N transmitters each transmitting one of N transmitted optically bound channels; a clock forwarding mechanism to transmit a transmitted optical clock signal to an opposing optical receiver; N receivers each receiving one of N received optically bound channels; and a clock recovery mechanism to receive a received optical clock signal from the opposing optical transmitter. A method and photonically integrated system are also disclosed. The optical transceiver, method, and system optimize system design of WDM highly parallelized transceivers with optical bound channels, a simplified clocking architecture, and boosted receiver sensitivity. The optical transceiver, method, and system include clock recovery followed by data recovery and can utilize integrate-and-dump optical receivers with a recovered clock.

    Abstract translation: 光收发器包括N个发送器，每个发送器发送N个发送的光学绑定信道之一; 时钟转发机制，用于将发送的光时钟信号发送到相对的光接收机; N个接收器，每个接收N个接收的光学绑定信道中的一个 以及时钟恢复机构，用于从相对的光发射机接收接收到的光时钟信号。 还公开了一种方法和光子集成系统。 光收发器，方法和系统优化了具有光限制通道的WDM高并行收发器的系统设计，简化的时钟架构和提高的接收器灵敏度。 光收发器，方法和系统包括时钟恢复，随后进行数据恢复，并且可以利用具有恢复时钟的集成和转储光接收器。

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