Latency-optimized physical coding sublayer

    公开(公告)号:US10110335B2

    公开(公告)日:2018-10-23

    申请号:US15299193

    申请日:2016-10-20

    摘要: A system for reducing latency in a networking application includes a first clock domain operating at a first clock frequency, where a media access control (MAC) sublayer sends data to a physical coding sublayer (PCS) utilizing the first clock domain. The system also includes a second clock domain operating at a second clock frequency, where data is transmitted on one or more physical medium attachment (PMA) lanes utilizing the second clock domain, and where the first clock frequency and the second clock frequency have a fixed ratio. Data is transmitted from the first clock domain to the second clock domain without buffering the data.

    Network controller—sideband interface port controller

    公开(公告)号:US09886404B2

    公开(公告)日:2018-02-06

    申请号:US14857978

    申请日:2015-09-18

    IPC分类号: G06F13/362 G06F13/40

    CPC分类号: G06F13/3625 G06F13/4068

    摘要: A network interface controller includes a media access controller and a host adapter. The host adapter includes a transmit route connected to receive an in-band packet from a host and further connected to transmit the in-band packet to the media access controller. The network interface controller also includes a sideband port controller connected to receive a sideband packet destined for a network from a sideband endpoint and further connected to transmit the sideband packet to the host adapter. The host adapter further includes a host buffer to store the in-band packet, a sideband buffer to store the sideband packet, and an arbiter connected to allow, at different times, the in-band packet to advance along the transmit route from the host buffer to the media access controller and the sideband packet to advance along the transmit route from the sideband buffer to the media access controller.