公开(公告)号：US11113204B2

公开(公告)日：2021-09-07

申请号：US16388478

申请日：2019-04-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bartholomew Blaner ,  Michael S. Siegel ,  Jeffrey A. Stuecheli ,  William J. Starke ,  Kenneth M. Valk ,  John D. Irish ,  Lakshminarayana Arimilli

IPC: G06F12/00 ,  G06F12/10 ,  G06F13/16 ,  G06F9/38 ,  G06F12/0817 ,  G06F12/1027 ,  G06F12/1045 ,  G06F3/06 ,  G06F13/28 ,  G06F9/455

Abstract: An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an accelerator functional unit and an effective address-based accelerator cache for buffering copies of data from the system memory of the coherent data processing system, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit includes request logic that, responsive to receipt on the first communication interface of a translation entry invalidation request, issues to the accelerator unit via the second communication interface an invalidation request that identifies an entry in the effective address-based accelerator cache to be invalidated utilizing a host tag identifying a storage location in the real address-based directory.

公开(公告)号：US20140204748A1

公开(公告)日：2014-07-24

申请号：US13747357

申请日：2013-01-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Claude Basso ,  Nikolaos Chrysos ,  Casimer M. DeCusatis ,  Mircea Gusat ,  Keshav G. Kamble ,  Cyriel J. Minkenberg ,  Fredy D. Neeser ,  Kenneth M. Valk

IPC: H04L12/56

CPC classification number: H04L47/527 ,  H04L47/521 ,  H04L47/6295

Abstract: In one embodiment, a system includes a processor and logic integrated with and/or executable by the processor, the logic being adapted to: receive a plurality of flows, each flow comprising packets of data, assign a service credit to each of the plurality of flows, assign a weight parameter to each of the plurality of flows, select a flow from a head of a first control queue unless the first control queue is empty or there is indication that the first control queue should be avoided, wherein a flow is selected from a head of a second control queue when the first control queue is empty or there is indication that the first control queue should be avoided, provide a number of units of service to the selected flow, and decrease the selected flow's service credit by an amount corresponding to the number of units of service provided thereto.

Abstract translation: 在一个实施例中，系统包括与处理器集成和/或可执行的处理器和逻辑，该逻辑适于：接收多个流，每个流包括数据分组，为多个 流量，为每个流量分配权重参数，从第一控制队列的头部选择一个流，除非第一控制队列为空，或者指示应该避免第一个控制队列，其中选择一个流 当第一控制队列为空时或者应该避免第一控制队列的指示时，从第二控制队列的头部向所选择的流提供多个服务单元，并且将所选流量的服务信用减少量 对应于提供给其的服务单元的数量。

公开(公告)号：US11095571B2

公开(公告)日：2021-08-17

申请号：US15802087

申请日：2017-11-02

Applicant: International Business Machines Corporation

Inventor： William J. Armstrong ,  Claude Basso ,  Chih-Jen Chang ,  Mircea Gusat ,  Cyriel J. Minkenberg ,  Fredy D. Neeser ,  Kenneth M. Valk

IPC: H04L12/927 ,  H04L12/46 ,  H04L12/931 ,  H04L12/911

Abstract: IEEE 802.1Q and Enhanced Transmission Selection provide only eight different traffic classes that may be used to control bandwidth in a particular physical connection (or link). Instead of relying only on these eight traffic classes to manage bandwidth, the embodiments discussed herein disclose using an Enhanced Transmission Selection scheduler that permits a network device to set the bandwidth for an individual virtual LAN. Allocating bandwidth in a port based on a virtual LAN ID permits a network device to allocate bandwidth to, e.g., millions of unique virtual LANs. Thus, this technique may increase the granular control of the network fabric and its performance.

公开(公告)号：US20180069802A1

公开(公告)日：2018-03-08

申请号：US15807463

申请日：2017-11-08

Applicant: International Business Machines Corporation

Inventor： Claude Basso ,  Nikolaos Chrysos ,  Casimer M. DeCusatis ,  Mircea Gusat ,  Keshav G. Kamble ,  Cyriel J. Minkenberg ,  Fredy D. Neeser ,  Kenneth M. Valk

IPC: H04L12/873 ,  H04L12/863

Abstract: In one embodiment, a method includes receiving a plurality of flows, each flow comprising packets of data and assigning a service credit to each of the plurality of flows. In addition, the method includes assigning a weight parameter to each of the plurality of flows, and selecting a flow from a head of a first control queue unless the first control queue is empty or there is indication that the first control queue should be avoided. A flow is selected from a head of a second control queue in response to a determination that the first control queue is empty or there is indication that the first control queue should be avoided. Additionally, the method includes providing a number of units of service to the selected flow. Moreover, the method includes decreasing the selected flow's service credit by an amount corresponding to the number of units of service provided thereto.

公开(公告)号：US20130194946A1

公开(公告)日：2013-08-01

申请号：US13708934

申请日：2012-12-08

Applicant: International Business Machines Corporation

Inventor： Claude Basso ,  Rolf Clauberg ,  Casimer M. DeCusatis ,  Mircea Gusat ,  Ronald P. Luijten ,  Fredy D. Neeser ,  Kenneth M. Valk

IPC: H04L12/26

CPC classification number: H04L43/00 ,  H04L43/08 ,  H04L47/30 ,  H04L47/56

Abstract: A system to improve a Converged Enhanced Ethernet network may include a controller having a computer processor connected to a layer 2 endpoint buffer. The system may also include a manager executing on the controller to monitor the layer 2 endpoint buffer by determining buffer data packet occupancy and/or rate of change in the buffer data packet occupancy. The system may further include a reporter to notify a congestion source of the layer 2 endpoint buffer based upon the buffer data packet occupancy and/or rate of change in the buffer data packet occupancy.

Abstract translation: 改进融合增强以太网的系统可以包括具有连接到层2端点缓冲器的计算机处理器的控制器。 系统还可以包括在控制器上执行的管理器，以通过确定缓冲器数据包占用率和/或缓冲器数据包占用率的变化率来监视第二层端点缓冲器。 该系统还可以包括报告员，以基于缓冲器数据包占用率和/或缓冲器数据包占用率的变化率来通知第2层端点缓冲器的拥塞源。

公开(公告)号：US09843529B2

公开(公告)日：2017-12-12

申请号：US14876528

申请日：2015-10-06

Applicant: International Business Machines Corporation

Inventor： Claude Basso ,  Nikolaos Chrysos ,  Casimer M. DeCusatis ,  Mircea Gusat ,  Keshav G. Kamble ,  Cyriel J. Minkenberg ,  Fredy D. Neeser ,  Kenneth M. Valk

IPC: H04L12/873 ,  H04L12/863

CPC classification number: H04L47/527 ,  H04L47/521 ,  H04L47/6295

Abstract: In one embodiment, a method includes selecting a flow from a head of a first control queue or a second control queue. The method also includes providing service to the selected flow. Moreover, the method includes decreasing a service credit of the selected flow by an amount corresponding to an amount of service provided to the selected flow. In another embodiment, a computer program product includes a computer readable storage medium having program code embodied therewith. The embodied program code is readable/executable by a device to select, by the device, a flow from a head of a first control queue or a second control queue. The embodied program code is also readable/executable to provide, by the device, service to the selected flow, and decrease, by the device, a service credit of the selected flow by an amount corresponding to an amount of service provided to the selected flow.

公开(公告)号：US09722810B2

公开(公告)日：2017-08-01

申请号：US14171015

申请日：2014-02-03

Applicant: International Business Machines Corporation

Inventor： Claude Basso ,  Nikolaos Chrysos ,  Cyriel Minkenberg ,  David A. Shedivy ,  Kenneth M. Valk ,  Brian T. Vanderpool

IPC: H04L12/26 ,  H04L12/18 ,  H04L12/801 ,  H04L12/823

CPC classification number: H04L12/1881 ,  H04L47/29 ,  H04L47/32

Abstract: A method for synchronizing multicast message subflows in a switched network includes associating, with a processing device, a first destination identifier corresponding to a multicast message with a first queue that corresponds to a first output port of a switching device, associating, with a processing device, a second destination identifier corresponding to the multicast message with a second queue that corresponds to a second output port of the switching device, pausing the first queue in response to a message counter corresponding to the first queue crossing a first predetermined threshold, and unpausing the first queue in response to the message counter crossing a second predetermined threshold, wherein the message counter indicates a quantity of data that has been forwarded by the first queue but remains to be forwarded by the second queue.

公开(公告)号：US09210095B2

公开(公告)日：2015-12-08

申请号：US13747357

申请日：2013-01-22

Applicant: International Business Machines Corporation

Inventor： Claude Basso ,  Nikolaos Chrysos ,  Casimer M. DeCusatis ,  Mircea Gusat ,  Keshav G. Kamble ,  Cyriel J. Minkenberg ,  Fredy D. Neeser ,  Kenneth M. Valk

IPC: H04L12/873

CPC classification number: H04L47/527 ,  H04L47/521 ,  H04L47/6295

Abstract: In one embodiment, a system includes a processor and logic integrated with and/or executable by the processor, the logic being adapted to: receive a plurality of flows, each flow comprising packets of data, assign a service credit to each of the plurality of flows, assign a weight parameter to each of the plurality of flows, select a flow from a head of a first control queue unless the first control queue is empty or there is indication that the first control queue should be avoided, wherein a flow is selected from a head of a second control queue when the first control queue is empty or there is indication that the first control queue should be avoided, provide a number of units of service to the selected flow, and decrease the selected flow's service credit by an amount corresponding to the number of units of service provided thereto.

Abstract translation: 在一个实施例中，系统包括与处理器集成和/或可执行的处理器和逻辑，该逻辑适于：接收多个流，每个流包括数据分组，为多个 流量，为每个流量分配权重参数，从第一控制队列的头部选择一个流，除非第一控制队列为空，或者指示应该避免第一个控制队列，其中选择一个流 当第一控制队列为空时或者应该避免第一控制队列的指示时，从第二控制队列的头部向所选择的流提供多个服务单元，并且将所选流量的服务信用减少量 对应于提供给其的服务单元的数量。

公开(公告)号：US11030110B2

公开(公告)日：2021-06-08

申请号：US16395942

申请日：2019-04-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael S. Siegel ,  Bartholomew Blaner ,  Jeffrey A. Stuecheli ,  William J. Starke ,  Derek E. Williams ,  Kenneth M. Valk ,  John D. Irish ,  Lakshminarayana Arimilli

IPC: G06F12/10 ,  G06F13/16 ,  G06F9/38 ,  G06F12/0817 ,  G06F12/1027 ,  G06F12/1045 ,  G06F3/06 ,  G06F13/28 ,  G06F9/455

Abstract: An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes request logic that communicates memory access requests and request responses with the accelerator unit. The request logic, responsive to receipt from the accelerator unit of a read-type request specifying an aliased second effective address of a target cache line, provides a request response including a host tag indicating that the accelerator unit has associated a different first effective address with the target cache line.

公开(公告)号：US20190163633A1

公开(公告)日：2019-05-30

申请号：US15826970

申请日：2017-11-30

Applicant: International Business Machines Corporation

Inventor： Kenneth M. Valk ,  Guy L. Guthrie ,  Derek E. Williams ,  Michael S. Siegel ,  John D. Irish

IPC: G06F12/0831 ,  G06F12/0864

Abstract: A claw-back request, received from an accelerator, is issued for an address line. While waiting for a response to the claw-back request, a cast-out push request with a matching address line is received. The cast-out push request is associated with a cache having a modified copy of the address line. A combined-response, associated with the cast-out push request, is received from a bus. Data associated with the modified copy of the address line is received from the cache. A claw-back response, with the data associated with the modified version of the address line, is issued to an accelerator.