公开(公告)号：US09070654B2

公开(公告)日：2015-06-30

申请号：US13868731

申请日：2013-04-23

Applicant: Cree, Inc.

Inventor： Davis Andrew McClure ,  Nathaniel Mark Williams

IPC: H01L29/34 ,  H01L29/66 ,  C30B29/36 ,  C30B33/00 ,  H01L21/02 ,  H01L21/04 ,  H01L21/306 ,  H01L29/16

CPC classification number: H01L29/34 ,  C30B29/36 ,  C30B33/00 ,  C30B33/005 ,  H01L21/02024 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/02538 ,  H01L21/02658 ,  H01L21/0445 ,  H01L21/30604 ,  H01L29/1608 ,  H01L29/66053

Abstract: A smoothing method for semiconductor material and semiconductor wafers produced by the method are disclosed. Semiconductor wafers with reduced atomic steps, as well with reduced scratches and subsurface defects can be produced. Such wafers feature an improved growth surface that can provide for the growth of an epilayer with reduced macroscopic defects and defect densities. A method of smoothing the surface of a wafer according to example embodiments of the invention includes planarizing the surface of a semiconductor wafer, and then oxidizing the wafer to achieve a specified thickness of oxide on the surface of the wafer. The oxide can then be stripped from the surface of the semiconductor wafer.

Abstract translation: 公开了通过该方法制造的半导体材料和半导体晶片的平滑方法。 可以制造具有降低的原子台阶的半导体晶片以及减少的划痕和次表面缺陷。 这样的晶片具有改善的生长表面，其可以提供具有减小的宏观缺陷和缺陷密度的外延层的生长。 根据本发明的示例性实施例的平滑晶片的表面的方法包括平面化半导体晶片的表面，然后氧化晶片以在晶片的表面上实现特定厚度的氧化物。 然后可以从半导体晶片的表面剥离氧化物。

公开(公告)号：US08963290B2

公开(公告)日：2015-02-24

申请号：US13990971

申请日：2010-12-28

Applicant: Ryuichi Toba ,  Yoshitaka Kadowaki ,  Meoung Whan Cho ,  Seog Woo Lee ,  Pil Guk Jang

Inventor： Ryuichi Toba ,  Yoshitaka Kadowaki ,  Meoung Whan Cho ,  Seog Woo Lee ,  Pil Guk Jang

IPC: H01L33/36 ,  H01L29/34 ,  H01L33/40 ,  H01L21/02 ,  H01L21/285 ,  H01L29/30 ,  H01L29/45 ,  H01L33/16 ,  H01L33/22 ,  H01L33/32 ,  H01S5/02 ,  H01S5/042 ,  H01S5/323 ,  H01S5/32 ,  H01L29/20

CPC classification number: H01L29/34 ,  H01L21/02664 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/30 ,  H01L29/452 ,  H01L33/16 ,  H01L33/22 ,  H01L33/32 ,  H01L33/40 ,  H01S5/0215 ,  H01S5/0217 ,  H01S5/0425 ,  H01S5/3202 ,  H01S5/32341

Abstract: The purpose of the present invention is to provide a good ohmic contact for an n-type Group-III nitride semiconductor. An n-type GaN layer and a p-type GaN layer are aequentially formed on a lift-off layer (growth step). A p-side electrode is formed on the top face of the p-type GaN layer. A copper block is formed over the entire area of the top face through a cap metal. Then, the lift-off layer is removed by making a chemical treatment (lift-off step). Then, a laminate structure constituted by the n-type GaN layer, with which the surface of the N polar plane has been exposed, and the p-type GaN layer is subjected to anisotropic wet etching (surface etching step). The N-polar surface after the etching has irregularities constituted by {10-1-1} planes. Then, an n-side electrode is formed on the bottom face of the n-type GaN layer (electrode formation step).

Abstract translation: 本发明的目的是为n型III族氮化物半导体提供良好的欧姆接触。 在剥离层（生长步骤）上同时形成n型GaN层和p型GaN层。 p型电极形成在p型GaN层的顶面上。 通过盖金属在顶面的整个区域上形成铜块。 然后，通过进行化学处理（剥离步骤）去除剥离层。 然后，对由n极GaN层的表面露出的n型GaN层和p型GaN层进行各向异性湿蚀刻（表面蚀刻工序）构成的层叠结构。 蚀刻后的N极性表面具有由{10-1-1}面构成的凹凸。 然后，在n型GaN层的底面上形成n侧电极（电极形成工序）。

公开(公告)号：US20150014824A1

公开(公告)日：2015-01-15

申请号：US14364900

申请日：2011-12-15

Applicant: Oleg Kononchuk

Inventor： Oleg Kononchuk

IPC: H01L21/3105 ,  H01L29/34

CPC classification number: H01L21/31053 ,  H01L21/02664 ,  H01L21/30 ,  H01L23/3178 ,  H01L29/2003 ,  H01L29/34 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a method for fabricating a substrate for a semiconductor device comprising an interface region between a first layer and a second layer having different electrical properties and an exposed surface, wherein at least the second layer includes defects and/or dislocations, the method comprising the steps of: a) removing material at one or more locations of the defects and/or dislocations, thereby forming pits, wherein the pits intersect the interface region, and b) passivating the pits. The invention also relates to a corresponding semiconductor device structure.

Abstract translation: 本发明涉及一种用于制造半导体器件的衬底的方法，其包括具有不同电性能和暴露表面的第一层和第二层之间的界面区域，其中至少第二层包括缺陷和/或位错， 方法包括以下步骤：a）在所述缺陷和/或位错的一个或多个位置处去除材料，从而形成凹坑，其中所述凹坑与所述界面区域相交，以及b）钝化所述凹坑。 本发明还涉及相应的半导体器件结构。

公开(公告)号：US20140327112A1

公开(公告)日：2014-11-06

申请号：US14350899

申请日：2011-10-14

Applicant: Jeffrey L. Libbert ,  Lu Fei

Inventor： Jeffrey L. Libbert ,  Lu Fei

IPC: H01L21/66 ,  H01L29/34

CPC classification number: H01L22/12 ,  G01N1/32 ,  H01L29/34

Abstract: Process for detecting grown-in-defects in a semiconductor silicon substrate. The process includes contacting a surface of the semiconductor silicon substrate with a gaseous acid in a reducing atmosphere at a temperature and duration sufficient to grow grown-in -defects disposed in the semiconductor silicon substrate to a size capable of being detected by an optical detection device.

Abstract translation: 用于检测半导体硅衬底中的生长缺陷的工艺。 该方法包括使半导体硅衬底的表面与还原气氛中的气态酸接触，所述气态温度和持续时间足以使设置在半导体硅衬底中的生长不良的生长到能够由光学检测装置检测的尺寸 。

公开(公告)号：US20140284627A1

公开(公告)日：2014-09-25

申请号：US14354858

申请日：2012-10-26

Applicant: LG INNOTEK CO., LTD.

Inventor： Moo Seong Kim

IPC: H01L21/02 ,  H01L29/34 ,  H01L29/16

CPC classification number: H01L21/02694 ,  C30B25/16 ,  C30B29/06 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02499 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/1608 ,  H01L29/34

Abstract: Disclosed is a method of manufacturing a thin film, the method including: growing an epitaxial layer on a surface of a wafer at a growth temperature, wherein the growing of the epitaxial layer comprises controlling a defect present on a surface of the wafer. Also, disclosed is a wafer including: a substrate; and an epitaxial layer located on the substrate, wherein a basal dislocation density of the epitaxial layer is equal to or less than 1/cm2.

Abstract translation: 公开了一种制造薄膜的方法，该方法包括：在生长温度下在晶片的表面上生长外延层，其中外延层的生长包括控制晶片表面上存在的缺陷。 此外，公开了一种晶片，包括：基板; 以及位于所述衬底上的外延层，其中所述外延层的基底位错密度等于或小于1 / cm 2。

公开(公告)号：US20140103492A1

公开(公告)日：2014-04-17

申请号：US14122356

申请日：2012-05-14

Applicant: Izumi Fusegawa ,  Ryoji Hoshi ,  Susumu Sonokawa ,  Hisayuki Saito

Inventor： Izumi Fusegawa ,  Ryoji Hoshi ,  Susumu Sonokawa ,  Hisayuki Saito

IPC: H01L21/02 ,  H01L29/34

CPC classification number: H01L21/02024 ,  C30B15/00 ,  C30B15/14 ,  C30B15/20 ,  C30B15/203 ,  C30B29/06 ,  C30B33/00 ,  C30B33/02 ,  H01L21/3221 ,  H01L29/30 ,  H01L29/34

Abstract: The present invention provides a method for producing a silicon wafer from a defect-free silicon single crystal grown by a CZ method, the method comprising: preparing a silicon wafer obtained by slicing the defect-free silicon single crystal and subjected to mirror-polishing; then performing a heat treatment step of subjecting the mirror-polished silicon wafer to heat treatment at a temperature of 500° C. or higher but 600° C. or lower for 4 hours or more but 6 hours or less; and performing a repolishing step of repolishing the silicon wafer after the heat treatment step such that a polishing amount becomes 1.5 μm or more. Therefore, it is an object to provide a method by which a silicon wafer can be produced at a high yield, the silicon wafer in which LPDs are reduced to a minimum, the silicon wafer with a low failure-incidence rate in an inspection step and a shipment stage.

Abstract translation: 本发明提供一种通过CZ方法生长的无缺陷硅单晶制造硅晶片的方法，该方法包括：制备通过对无缺陷的硅单晶进行切片并进行镜面抛光获得的硅晶片; 然后进行热处理步骤，使经镜面抛光的硅晶片在500℃以上但600℃以下的温度下进行4小时以上6小时以下的热处理; 并且在热处理步骤之后执行重新抛光硅晶片的重新抛光步骤，使得抛光量变为1.5μm以上。 因此，本发明的目的是提供一种可以以高产率制造硅晶片的方法，将LPD降低到最小的硅晶片，在检查步骤中具有低故障发生率的硅晶片，以及 出货阶段

公开(公告)号：US08692342B2

公开(公告)日：2014-04-08

申请号：US13181957

申请日：2011-07-13

Applicant: Sechung Oh ,  Jangeun Lee ,  Woojin Kim ,  Heeju Shin

Inventor： Sechung Oh ,  Jangeun Lee ,  Woojin Kim ,  Heeju Shin

IPC: H01L29/82 ,  H01L43/00 ,  H01L23/552 ,  H01L29/34 ,  H01L29/74 ,  H01L31/111

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Provided are magnetic memory devices, electronic systems and memory cards including the same, methods of manufacturing the same, and methods of controlling a magnetization direction of a magnetic pattern. In a magnetic memory device, atomic-magnetic moments non-parallel to one surface of a free pattern increase in the free pattern. Therefore, critical current density of the magnetic memory device may be reduced, such that power consumption of the magnetic memory device is reduced or minimized and/or the magnetic memory device is improved or optimized for a higher degree of integration.

Abstract translation: 提供了磁存储器件，电子系统和包括其的存储卡，其制造方法以及控制磁性图案的磁化方向的方法。 在磁存储器件中，不平行于自由图案的一个表面的原子磁矩在自由图案中增加。 因此，可以减小磁存储器件的临界电流密度，使得磁存储器件的功耗被降低或最小化，和/或磁存储器件被改进或优化以达到更高的集成度。

公开(公告)号：US20140042594A1

公开(公告)日：2014-02-13

申请号：US13570426

申请日：2012-08-09

Applicant: Stephen P. Ayotte ,  David J. Hill ,  Glen E. Richard ,  Timothy M. Sullivan ,  Heather M. Truax

Inventor： Stephen P. Ayotte ,  David J. Hill ,  Glen E. Richard ,  Timothy M. Sullivan ,  Heather M. Truax

IPC: H01L21/312 ,  H01L29/34

CPC classification number: H01L21/302 ,  H01L21/31058 ,  H01L21/312 ,  H01L22/12 ,  H01L22/20 ,  H01L23/3171 ,  H01L23/3178 ,  H01L29/32 ,  H01L29/34 ,  H01L2224/13 ,  H01L2924/10158

Abstract: Aspects of the disclosure provide a method of inhibiting crack propagation in a silicon wafer. In one embodiment, a method of repairing an imperfection on a surface of a semiconductor device is disclosed. The method includes: screening for imperfections on a surface of a silicon wafer of a semiconductor device; and in response to at least one imperfection on the surface of the silicon wafer, depositing a material on the surface of the silicon wafer.

Abstract translation: 本公开的方面提供了抑制硅晶片中裂纹扩展的方法。 在一个实施例中，公开了修复半导体器件表面上的缺陷的方法。 该方法包括：筛选半导体器件的硅晶片的表面上的缺陷; 并且响应于硅晶片的表面上的至少一个缺陷，在硅晶片的表面上沉积材料。

公开(公告)号：US20140015105A1

公开(公告)日：2014-01-16

申请号：US13990971

申请日：2010-12-28

Applicant: Ryuichi Toba ,  Yoshitaka Kadowaki ,  Meoung Whan Cho ,  Seog Woo Lee ,  Pil Guk Jang

Inventor： Ryuichi Toba ,  Yoshitaka Kadowaki ,  Meoung Whan Cho ,  Seog Woo Lee ,  Pil Guk Jang

IPC: H01L29/34 ,  H01L21/02

CPC classification number: H01L29/34 ,  H01L21/02664 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/30 ,  H01L29/452 ,  H01L33/16 ,  H01L33/22 ,  H01L33/32 ,  H01L33/40 ,  H01S5/0215 ,  H01S5/0217 ,  H01S5/0425 ,  H01S5/3202 ,  H01S5/32341

Abstract: The purpose of the present invention is to provide a good ohmic contact for an n-type Group-III nitride semiconductor. An n-type GaN layer and a p-type GaN layer are aequentially formed on a lift-off layer (growth step). A p-side electrode is formed on the top face of the p-type GaN layer. A copper block is formed over the entire area of the top face through a cap metal. Then, the lift-off layer is removed by making a chemical treatment (lift-off step). Then, a laminate structure constituted by the n-type GaN layer, with which the surface of the N polar plane has been exposed, and the p-type GaN layer is subjected to anisotropic wet etching (surface etching step). The N-polar surface after the etching has irregularities constituted by {10-1-1} planes. Then, an n-side electrode is formed on the bottom face of the n-type GaN layer (electrode formation step).

Abstract translation: 本发明的目的是为n型III族氮化物半导体提供良好的欧姆接触。 在剥离层（生长步骤）上同时形成n型GaN层和p型GaN层。 p型电极形成在p型GaN层的顶面上。 通过帽金属在顶面的整个区域上形成铜块。 然后，通过进行化学处理（剥离步骤）去除剥离层。 然后，对由n极GaN层的表面露出的n型GaN层和p型GaN层进行各向异性湿蚀刻（表面蚀刻工序）构成的层叠结构。 蚀刻后的N极性表面具有由{10-1-1}面构成的凹凸。 然后，在n型GaN层的底面上形成n侧电极（电极形成工序）。

公开(公告)号：US20130234162A1

公开(公告)日：2013-09-12

申请号：US13868731

申请日：2013-04-23

Applicant: CREE, INC.

Inventor： Davis Andrew McClure ,  Nathaniel Mark Williams

IPC: H01L29/34

CPC classification number: H01L29/34 ,  C30B29/36 ,  C30B33/00 ,  C30B33/005 ,  H01L21/02024 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/02538 ,  H01L21/02658 ,  H01L21/0445 ,  H01L21/30604 ,  H01L29/1608 ,  H01L29/66053

Abstract: A smoothing method for semiconductor material and semiconductor wafers produced by the method are disclosed. Semiconductor wafers with reduced atomic steps, as well with reduced scratches and subsurface defects can be produced. Such wafers feature an improved growth surface that can provide for the growth of an epilayer with reduced macroscopic defects and defect densities. A method of smoothing the surface of a wafer according to example embodiments of the invention includes planarizing the surface of a semiconductor wafer, and then oxidizing the wafer to achieve a specified thickness of oxide on the surface of the wafer. The oxide can then be stripped from the surface of the semiconductor wafer.

Abstract translation: 公开了通过该方法制造的半导体材料和半导体晶片的平滑方法。 可以制造具有降低的原子台阶的半导体晶片以及减少的划痕和次表面缺陷。 这样的晶片具有改善的生长表面，其可以提供具有减小的宏观缺陷和缺陷密度的外延层的生长。 根据本发明的示例性实施例的平滑晶片的表面的方法包括平面化半导体晶片的表面，然后氧化晶片以在晶片的表面上实现特定厚度的氧化物。 然后可以从半导体晶片的表面剥离氧化物。