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公开(公告)号：US20230345845A1
公开(公告)日：2023-10-26
申请号：US18136837
申请日：2023-04-19
Applicant: Quantum Designed Materials Ltd.
Inventor： Refael GATT
IPC: H10N60/85 , C23C16/02 , C23C16/40 , C23C16/455 , C23C16/56 , C30B23/00 , C30B23/02 , C30B25/16 , C30B25/18 , C30B29/22 , H01B1/08 , H10N60/01 , H10N60/12
CPC classification number: H10N60/85 , C23C16/0272 , C23C16/408 , C23C16/45531 , C23C16/56 , C30B23/005 , C30B23/025 , C30B25/165 , C30B25/183 , C30B29/22 , H01B1/08 , H10N60/01 , H10N60/12
Abstract: A superconducting article includes a substrate and a superconducting metal oxide film formed on the substrate. The metal oxide film including ions of an alkali metal, ions of a transition metal, and ions of an alkaline earth metal or a rare earth metal. For instance, the metal oxide film can include Rb ions, La ions, and Cu ions. The superconducting metal oxide film can have a critical temperature for onset of superconductivity of greater than 250 K, e.g., greater than room temperature.
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公开(公告)号：US11696517B2
公开(公告)日：2023-07-04
申请号：US17349281
申请日：2021-06-16
Applicant: NEC Corporation
Inventor： Kenji Nanba , Ayami Yamaguchi , Akira Miyata , Katsumi Kikuchi , Suguru Watanabe , Takanori Nishi , Hideyuki Satou
Abstract: A quantum device (100) includes: an interposer (112); a quantum chip (111); and a connection part (130) that is provided between the interposer (112) and the quantum chip (111) and electrically connects a wiring layer of the interposer (112) to a wiring layer of the quantum chip (111), in which the connection part (130) includes: a plurality of pillars (131) arranged on a main surface of the interposer (112); and a metal film (132) provided on a surface of the plurality of pillars (131) in such a way that it contacts the wiring layer of the quantum chip (111) and the thickness of the metal film at outer peripheral parts of the tip of each of the plurality of pillars (131) becomes larger than the thickness of the metal film at a center part of the tip of each of the plurality of pillars (131).
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公开(公告)号：US11690301B2
公开(公告)日：2023-06-27
申请号：US17405448
申请日：2021-08-18
Applicant: Google LLC
Inventor： Anthony Edward Megrant
CPC classification number: H10N60/83 , G06N10/00 , H10N60/01 , H10N69/00 , H01L21/76891 , H10N60/0912 , H10N60/10 , H10N60/855
Abstract: A qubit coupling device includes: a dielectric substrate including a trench; a first superconductor layer on a surface of the dielectric substrate where an edge of the first superconductor layer extends along a first direction and at least a portion of the superconductor layer is in contact with the surface of the dielectric substrate, and where the superconductor layer is formed from a superconductor material exhibiting superconductor properties at or below a corresponding critical temperature; a length of the trench within the dielectric substrate is adjacent to and extends along an edge of the first superconductor layer in the first direction, and where the electric permittivity of the trench is less than the electric permittivity of the dielectric substrate.
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公开(公告)号：US20230180633A1
公开(公告)日：2023-06-08
申请号：US17924037
申请日：2021-04-14
Inventor： Takahiro Mori , Atsushi Yagishita
CPC classification number: H10N60/128 , H10N60/11 , H10N60/01
Abstract: To suppress a leakage current caused by a gate of a tunnel field effect transistor included in a silicon spin quantum bit device, the silicon spin quantum bit device is provided including a tunnel field effect transistor having a gate, a source, and a drain, a quantum gate operation mechanism for spin control, which is provided under the tunnel field effect transistor, and an inter-qubit coupler for coupling a channel of the tunnel field effect transistor with a channel of a tunnel field effect transistor included in another quantum bit device. Further, the gate is made wider in width than the channel and is partly formed on the inter-qubit coupler.
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55.发明公开公开(公告)号：US20230164904A1
公开(公告)日：2023-05-25
申请号：US17898065
申请日：2022-08-29
Applicant: FERMI RESEARCH ALLIANCE, LLC
Inventor： Alexander Romanenko , Sam Posen , Anna Grassellino
Abstract: A system and method for treating a cavity comprises preparing a superconducting radio frequency (SRF) cavity for removal of a dielectric layer from on an inner surface of the SRF cavity, subjecting the SRF cavity to a heat treatment in order to remove the dielectric layer from the inner surface of the SRF cavity, and preventing the development of a new dielectric layer on the inner surface of the SRF cavity by preventing an interaction between the inner surface of the SRF cavity and atmospheric gasses.
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Patent Agency Ranking
公开(公告)号：US20230154639A1
公开(公告)日：2023-05-18
申请号：US17917669
申请日：2021-02-11
Inventor： Jeremy Levy
IPC: G21K5/04 , H01J37/317 , H01J37/28 , H01J37/147 , H10N52/01 , H10N60/30 , H10N60/01 , H10N70/20 , H10N70/00
CPC classification number: G21K5/04 , H01J37/3174 , H01J37/28 , H01J37/147 , H10N52/01 , H10N60/30 , H10N60/01 , H10N70/257 , H10N70/041 , H01J2237/004
Abstract: Described is a method comprising directing an ultra-low voltage electron beam to a surface of a first insulating layer. The first insulating layer is disposed on a second insulating layer. The method includes modifying, by the application of the ultra-low voltage electron beam, the surface of the first insulating layer to selectively switch an interface between a first state having a first electronic property and a second state having a second electronic property.
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公开(公告)号：US20240357946A1
公开(公告)日：2024-10-24
申请号：US18520462
申请日：2023-11-27
Applicant: PsiQuantum Corp.
Inventor： Faraz Najafi
Abstract: A device includes a superconductor layer and a piezoelectric layer positioned adjacent to the superconductor layer. The piezoelectric layer is configured to apply a first strain to the superconductor layer in response to receiving a first voltage that is below a predefined voltage threshold and to apply a second strain to the superconductor layer in response to receiving a second voltage that is above the predefined voltage threshold. While the device is maintained below a superconducting threshold temperature for the superconductor layer and is supplied with current below a superconducting threshold current for the superconductor layer, the superconductor layer is configured to 1) operate in a superconducting state when the piezoelectric layer applies the first strain to the superconductor layer and 2) operate in an insulating state when the piezoelectric layer applies the second strain to the superconductor layer.
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公开(公告)号：US20240341203A1
公开(公告)日：2024-10-10
申请号：US18579259
申请日：2021-07-12
Applicant: Microsoft Technology Licensing, LLC
Inventor： Charles Masamed MARCUS , Andreas Simon PÖSCHL , Alisa DANILENKO
CPC classification number: H10N60/128 , H10N60/01 , H10N60/11
Abstract: A semiconductor-superconductor hybrid device comprises a semiconductor component which, when in use, comprises a channel in the form of a nanowire; a superconductor component capable of inducing superconductivity in the semiconductor component by proximity effect; and an array of finger gates. The finger gates are individually operable to apply respective electrostatic fields to respective segments of the channel. The array of finger gates allows for localized control over electrical potentials in the corresponding segments of the nanowire. Also provided are methods of fabricating and operating the semiconductor-superconductor hybrid device.
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公开(公告)号：US12113123B2
公开(公告)日：2024-10-08
申请号：US18070765
申请日：2022-11-29
Inventor： Robert A. Makin, III , Steven Michael Durbin
CPC classification number: H01L29/66893 , H01L22/14 , H10N60/01 , H10N60/0912 , H10N60/12
Abstract: A method of fabricating a superconducting device includes determining a target transition temperature and utilizing a predefined quantitative relationship between superconducting transition temperature and an order parameter for at least one superconducting material composition is utilized to select a superconductor material composition that is capable of providing a target transition temperature. Process parameters may be controlled to form a superconductor device comprising at least one superconductor material having a material composition providing the target transition temperature.
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公开(公告)号：US12041857B2
公开(公告)日：2024-07-16
申请号：US17906427
申请日：2020-03-30
Applicant: Microsoft Technology Licensing, LLC
Inventor： Roy Leonardus Maria Op Het Veld , Jason Petros Heinrich Jung , Petrus Johannes Van Veldhoven
CPC classification number: H10N60/01 , H03K17/92 , H10N60/10 , B82Y10/00 , B82Y40/00 , G06N10/80 , H10N60/83
Abstract: A method of fabricating semiconductor-superconductor nanowires, comprising: forming a first mask amorphous mask having first openings over trenches in a substrate; forming a monocrystalline conducting material in the first openings by selective area growth, thus forming gates for the nanowires in the trenches pf the substrate; forming a second mask over the substrate and gates, the second mask also being amorphous and having a pattern of second openings; forming an insulating crystalline buffer in the second openings; forming a crystalline semiconductor material on the buffer in the second openings by selective area growth in order to form the cores of the nanowires, wherein the gates intersect with the cores in the plane of the substrate; and forming the coating of superconductor material over at least part of each of the cores.
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