公开(公告)号：US11830876B2

公开(公告)日：2023-11-28

申请号：US17451415

申请日：2021-10-19

Applicant: Tokyo Electron Limited

Inventor： H. Jim Fulford ,  Mark I. Gardner ,  Partha Mukhopadhyay

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/823871 ,  H01L23/528 ,  H01L29/7827

Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack of insulating layers and interconnect layers that are positioned alternatingly over a substrate. The semiconductor device includes a channel structure extending from the substrate and further through the insulating layers and the interconnect layers. The channel structure includes a first channel section positioned over the substrate and coupled to a first group of the interconnect layers, and a second channel section positioned over the first channel section and coupled to a second group of the interconnect layers. The semiconductor device also includes a plurality of contact structures extending from and coupled to the interconnect layers in a staircase configuration such that each of the plurality of contact structures extends from a respective interconnect layer.

公开(公告)号：US20230371242A1

公开(公告)日：2023-11-16

申请号：US18029660

申请日：2021-10-04

Applicant: Tokyo Electron Limited

Inventor： Song yun KANG ,  Hyuck Soo YANG

IPC: H10B12/00 ,  H01L29/78

CPC classification number: H10B12/482 ,  H10B12/05 ,  H10B12/488 ,  H10B12/033 ,  H01L29/7827

Abstract: A method of making a semiconductor device that includes forming a vertical access transistor including forming bit lines in a first direction on a substrate, forming a polysilicon pillar as a sacrificial pillar over each bit line of the bit lines, forming a gate oxide on side surfaces of the polysilicon pillar, forming a word line, in a second direction, on the polysilicon pillar with the gate oxide interposed between the word line and the polysilicon pillar, the second direction being not substantially parallel to the first direction, after forming the word line, removing the polysilicon pillar so as to leave a vertical void in place of the polysilicon pillar, filling the vertical void with an oxide semiconductor that serves as a channel for the vertical access transistor; and forming a cell capacitor over the channel of the vertical access transistor.

公开(公告)号：US11804520B2

公开(公告)日：2023-10-31

申请号：US17464296

申请日：2021-09-01

Applicant: ROHM CO., LTD.

Inventor： Yuki Nakano ,  Ryota Nakamura

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/16 ,  H01L27/088 ,  H01L21/04 ,  H01L29/04 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/063 ,  H01L21/046 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0607 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/7811

Abstract: A semiconductor device includes a semiconductor layer made of a wide bandgap semiconductor and including a gate trench; a gate insulating film formed on the gate trench; and a gate electrode embedded in the gate trench to be opposed to the semiconductor layer through the gate insulating film. The semiconductor layer includes a first conductivity type source region; a second conductivity type body region; a first conductivity type drift region; a second conductivity type first breakdown voltage holding region; a source trench passing through the first conductivity type source region and the second conductivity type body region from the front surface and reaching a drain region; and a second conductivity type second breakdown voltage region selectively formed on an edge portion of the source trench where the sidewall and the bottom wall thereof intersect with each other in a parallel region of the source trench.

公开(公告)号：US11799027B2

公开(公告)日：2023-10-24

申请号：US16992558

申请日：2020-08-13

Applicant: Micron Technology, Inc.

Inventor： Yuki Munetaka ,  Kazuo Ogawa

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L29/7827 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/4238 ,  H01L29/42356 ,  H01L29/66666 ,  H01L29/0653

Abstract: A semiconductor device includes an active region which is surrounded by a device isolation region on a semiconductor substrate and which extends in a first direction; a silicon pillar which separates the active region along the first direction into a first lower diffusion layer and a second lower diffusion layer; a first gate electrode covering a first side face of the silicon pillar which is located on a side of the first lower diffusion layer; a second gate electrode covering a second side face of the silicon pillar which is located on a side of the second lower diffusion layer; a conductive layer provided on a top face of the silicon pillar; and a device isolation insulating film contacting with a third side face of the silicon pillar which is different from the first side face and the second side face.

公开(公告)号：US11791408B2

公开(公告)日：2023-10-17

申请号：US17744308

申请日：2022-05-13

Applicant: Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

Inventor： Kenya Kobayashi

IPC: H01L29/78 ,  H01L29/45

CPC classification number: H01L29/7827 ,  H01L29/45

Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, second, and third semiconductor regions, an insulating part, a conductive part, and a gate electrode. The first semiconductor region is provided on the first electrode and is electrically connected to the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The insulating part is provided on the first electrode. The conductive part is provided in the insulating part and is arranged with the first semiconductor region. The gate electrode is provided in the insulating part. The gate electrode is positioned above the conductive part and is arranged with the second semiconductor region. The second electrode is provided on the third semiconductor region and the insulating part, and is electrically connected to the third semiconductor region.

公开(公告)号：US20230326959A1

公开(公告)日：2023-10-12

申请号：US18172627

申请日：2023-02-22

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Ryo TANAKA ,  Shinya TAKASHIMA ,  Katsunori UENO

IPC: H01L29/06 ,  H01L29/20 ,  H01L29/207 ,  H01L29/78 ,  H01L29/10 ,  H01L21/265

CPC classification number: H01L29/0615 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/7827 ,  H01L29/1095 ,  H01L21/2654

Abstract: An impurity region of P-type that the field effect transistor of the nitride semiconductor device includes has a peak position at which concentration of P-type impurities reaches a maximum at a position located away from an interface with a gate insulating film. The impurity region has an inflection point at which concentration of the P-type impurities changes from increase to decrease toward the interface or a rate of decrease in the concentration of the P-type impurities increases toward the interface at a position located between the interface and the peak position.

公开(公告)号：US11784096B2

公开(公告)日：2023-10-10

申请号：US17539669

申请日：2021-12-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Choonghyun Lee ,  Pouya Hashemi ,  Takashi Ando

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/225 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/10 ,  H01L29/165 ,  H01L29/04 ,  H01L21/324

CPC classification number: H01L21/823885 ,  H01L21/0262 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/225 ,  H01L21/324 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/04 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method for fabricating a semiconductor device including vertical transport fin field-effect transistors (VTFETs) is provided. The method includes forming a bottom spacer on a first device region associated with a first VTFET and a second device region associated with a second VTFET, forming a liner on the bottom spacer, on a first fin structure including silicon germanium (SiGe) formed in the first device region and on a second fin structure including SiGe formed in the second device region, and forming crystalline Ge having a hexagonal structure from the SiGe by employing a Ge condensation process to orient a (111) direction of the crystalline Ge in a direction of charge flow for a VTFET.

公开(公告)号：US20230317817A1

公开(公告)日：2023-10-05

申请号：US18191177

申请日：2023-03-28

Applicant: SEIKO EPSON CORPORATION

Inventor： Hiroyuki SHIMADA

IPC: H01L29/51 ,  H01L29/78

CPC classification number: H01L29/517 ,  H01L29/7827

Abstract: A semiconductor device includes a first semiconductor portion and a second semiconductor portion having the same conductivity type and arranged along a first direction, a third semiconductor portion provided between the first semiconductor portion and the second semiconductor portion and having a lower impurity concentration than the first semiconductor portion and the second semiconductor portion, a fourth semiconductor portion provided between the second semiconductor portion and the third semiconductor portion and having a lower impurity concentration than the first semiconductor portion and the second semiconductor portion, a gate insulating layer and a gate electrode provided in a second direction of the third semiconductor portion, the second direction intersecting the first direction, and a dielectric portion provided in the second direction of the fourth semiconductor portion, wherein the dielectric portion is formed of a material having a larger band gap and a larger relative permittivity than a material forming the fourth semiconductor portion, and a depletion layer is formed at the fourth semiconductor portion when a predetermined voltage is applied to the gate electrode.

公开(公告)号：US11769809B2

公开(公告)日：2023-09-26

申请号：US17083026

申请日：2020-10-28

Applicant: Sang-Yun Lee

Inventor： Sang-Yun Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/792 ,  H10B43/27 ,  H01L29/423 ,  H01L25/18 ,  H01L29/40 ,  H01L29/06 ,  H10B12/00 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L29/4234 ,  H01L25/18 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7926 ,  H10B12/05 ,  H10B12/31 ,  H10B12/50 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

公开(公告)号：US11764259B2

公开(公告)日：2023-09-19

申请号：US17384307

申请日：2021-07-23

Applicant: International Business Machines Corporation

Inventor： Chen Zhang ,  Tenko Yamashita ,  Xin Miao ,  Wenyu Xu ,  Kangguo Cheng

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L29/41741 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66666 ,  H01L29/7827

Abstract: A vertical field-effect transistor includes a substrate comprising a semiconductor material; a first set of fins formed from the semiconductor material and extending vertically with respect to the substrate; and a second set of fins extending vertically with respect to the substrate, wherein ones of the second set of fins abut ones of the first set of fins. The second set of fins comprises a dielectric material.