公开(公告)号：US20160268252A1

公开(公告)日：2016-09-15

申请号：US14901579

申请日：2013-08-26

申请人： Jun Saito ,  Satoru Machida ,  Yusuke Yamashita

发明人： Jun Saito ,  Satoru Machida ,  Yusuke Yamashita

IPC分类号： H01L27/06 ,  H01L29/739 ,  H01L29/10 ,  H01L29/872

CPC分类号： H01L27/0629 ,  H01L27/0727 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/47 ,  H01L29/7397 ,  H01L29/872

摘要： A technology capable of suppressing a fluctuation in voltage in a diode region is provided. A resistance value between the emitter electrode and the lower body region is lower than a resistance value between the anode electrode and the lower anode region when the semiconductor device operates as a diode. A quantity of holes between the emitter electrode and the second barrier region is smaller than a quantity of holes between the anode electrode and the first barrier region.

摘要翻译： 提供了能够抑制二极管区域中的电压波动的技术。 当半导体器件作为二极管工作时，发射电极和下体区域之间的电阻值低于阳极电极和下阳极区域之间的电阻值。 发射电极和第二阻挡区域之间的一定数量的孔小于阳极电极和第一阻挡区域之间的空穴量。

公开(公告)号：US09425312B2

公开(公告)日：2016-08-23

申请号：US14311401

申请日：2014-06-23

申请人： International Business Machines Corporation

发明人： Anirban Basu ,  Bahman Hekmatshoartabari ,  Davood Shahrjerdi

IPC分类号： H01L21/337 ,  H01L29/78 ,  H01L29/06 ,  H01L29/04 ,  H01L29/267 ,  H01L29/66 ,  H01L21/306 ,  H01L29/10 ,  H01L21/28 ,  H01L29/08 ,  H01L21/265 ,  H01L21/308 ,  H01L21/02 ,  H01L29/739

CPC分类号： H01L29/7848 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28255 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/308 ,  H01L21/3085 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/083 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1041 ,  H01L29/267 ,  H01L29/66477 ,  H01L29/66977 ,  H01L29/7391

摘要： Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and III-N source regions are provided for low power operations. A broken-band heterojunction is formed by the source and channel regions of the transistors. Fabrication methods include selective anisotropic wet-etching of a silicon substrate followed by epitaxial deposition of III-N material and/or germanium implantation of the substrate followed by the epitaxial deposition of the III-N material.

摘要翻译： 包括硅，锗或硅锗通道和III-N源极区域的隧道化场效应晶体管用于低功率操作。 由晶体管的源极和沟道区域形成断带异质结。 制造方法包括硅衬底的选择性各向异性湿蚀刻，然后III-N材料的外延沉积和/或衬底的锗注入，然后III-N材料的外延沉积。

公开(公告)号：US09324815B2

公开(公告)日：2016-04-26

申请号：US14702070

申请日：2015-05-01

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Tsuneo Ogura ,  Tomoko Matsudai ,  Yuuichi Oshino ,  Yoshiko Ikeda ,  Kazutoshi Nakamura ,  Ryohei Gejo

IPC分类号： H01L29/08 ,  H01L29/36 ,  H01L29/10 ,  H01L29/861 ,  H01L29/739 ,  H01L29/78 ,  H01L29/872 ,  H01L29/06

CPC分类号： H01L29/36 ,  H01L29/0626 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/0839 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/402 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7806 ,  H01L29/7839 ,  H01L29/861 ,  H01L29/872

摘要： According one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode and being in contact with the first electrode; a second semiconductor layer including a first part and a second part, and the second part being contact with the first electrode, and the second semiconductor layer having an effective impurity concentration lower than an effective impurity concentration in the first semiconductor layer; a third semiconductor layer provided between the second semiconductor layer and the second electrode, and having an effective impurity concentration lower than an effective impurity concentration in the second semiconductor layer; and a fourth semiconductor layer provided between the third semiconductor layer and the second electrode, and being in contact with the second electrode.

公开(公告)号：US20160099343A1

公开(公告)日：2016-04-07

申请号：US14503587

申请日：2014-10-01

申请人： GLOBALFOUNDRIES Inc.

发明人： Bartlomiej Jan Pawlak

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L29/205 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165

CPC分类号： H01L29/66977 ,  H01L21/823418 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/66356 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/7827 ,  H01L29/7848

摘要： One illustrative method of forming a TFET device includes forming a first semiconductor material that extends for a full length of a drain region, a gate region and a source region of the device, masking the drain region while exposing at least a portion of the gate region and exposing the source region, forming a second semiconductor material above the gate region and above the source region, forming a third semiconductor material above the second semiconductor material and above the gate region and above the source region, the third semiconductor material being doped with an opposite type of dopant material than in the first semiconductor material, masking the drain region, and forming a gate structure above at least a portion of the exposed gate region.

摘要翻译： 形成TFET器件的一个示例性方法包括形成第一半导体材料，其延伸器件的漏极区域，栅极区域和源极区域的整个长度，在暴露栅极区域的至少一部分的同时掩蔽漏极区域 并且在所述源极区域的上方形成第二半导体材料，在所述源极区域的上方形成第二半导体材料，在所述栅极区域的上方，在所述源极区域的上方形成第三半导体材料，在所述第二半导体材料的上方形成第三半导体材料， 相反类型的掺杂剂材料比第一半导体材料中的掩模，掩蔽漏极区域，以及在暴露的栅极区域的至少一部分上方形成栅极结构。

公开(公告)号：US20150372141A1

公开(公告)日：2015-12-24

申请号：US14311401

申请日：2014-06-23

申请人： International Business Machines Corporation

发明人： Anirban Basu ,  Bahman Hekmatshoartabari ,  Davood Shahrjerdi

IPC分类号： H01L29/78 ,  H01L29/04 ,  H01L29/267 ,  H01L29/66 ,  H01L21/308 ,  H01L21/02 ,  H01L29/10 ,  H01L21/28 ,  H01L29/08 ,  H01L21/265 ,  H01L29/06 ,  H01L21/306

CPC分类号： H01L29/7848 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28255 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/308 ,  H01L21/3085 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/083 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1041 ,  H01L29/267 ,  H01L29/66477 ,  H01L29/66977 ,  H01L29/7391

摘要： Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and III-N source regions are provided for low power operations. A broken-band heterojunction is formed by the source and channel regions of the transistors. Fabrication methods include selective anisotropic wet-etching of a silicon substrate followed by epitaxial deposition of III-N material and/or germanium implantation of the substrate followed by the epitaxial deposition of the III-N material.

摘要翻译： 包括硅，锗或硅锗通道和III-N源极区域的隧道化场效应晶体管用于低功率操作。 由晶体管的源极和沟道区域形成断带异质结。 制造方法包括硅衬底的选择性各向异性湿蚀刻，然后III-N材料的外延沉积和/或衬底的锗注入，然后III-N材料的外延沉积。

公开(公告)号：US20150340489A1

公开(公告)日：2015-11-26

申请号：US14568886

申请日：2014-12-12

申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION

发明人： Deyuan XIAO

IPC分类号： H01L29/78 ,  H01L29/786 ,  H01L29/66

CPC分类号： H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/083 ,  H01L29/66356 ,  H01L29/7391

摘要： A fin tunneling field effect transistor (TFET) is disclosed. The fin TFET includes a semiconductor body extending in a first direction on a substrate, wherein the semiconductor body constitutes a channel of the fin TFET. The fin TFET also includes a source and a drain disposed at opposite ends of the semiconductor body, wherein the source is doped with a first dopant type and the drain is doped with a second dopant type, and the first dopant type is different from the second dopant type. The fin TFET further includes a gate disposed on at least two sides of the channel, wherein a portion of the source is disposed in contact with a portion of the channel.

摘要翻译： 公开了一种鳍式隧道场效应晶体管（TFET）。 翅片TFET包括在衬底上沿第一方向延伸的半导体本体，其中半导体主体构成鳍状TFET的沟道。 翅片TFET还包括设置在半导体本体的相对端处的源极和漏极，其中源极掺杂有第一掺杂剂类型，并且漏极掺杂有第二掺杂剂类型，并且第一掺杂剂类型与第二掺杂剂类型不同 掺杂剂类型。 翅片TFET还包括设置在通道的至少两侧的门，其中源的一部分设置成与通道的一部分接触。

公开(公告)号：US09153674B2

公开(公告)日：2015-10-06

申请号：US12421322

申请日：2009-04-09

申请人： Hans-Joachim Schulze

发明人： Hans-Joachim Schulze

IPC分类号： H01L29/739 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/7395 ,  H01L29/0615 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/7393

摘要： A semiconductor device is disclosed. One embodiment provides a cell area and a junction termination area at a first side of a semiconductor zone of a first conductivity type. At least one first region of a second conductivity type is formed at a second side of the semiconductor zone. The at least one first region is opposed to the cell area region. At least one second region of the second conductivity type is formed at the second side of the semiconductor zone. The at least one second region is opposed to the cell area region and has a lateral dimension smaller than the at least first region.

摘要翻译： 公开了一种半导体器件。 一个实施例提供在第一导电类型的半导体区域的第一侧处的单元区域和结端接区域。 至少一个第二导电类型的第一区域形成在半导体区域的第二侧。 所述至少一个第一区域与所述单元区域区域相对。 第二导电类型的至少一个第二区域形成在半导体区域的第二侧。 所述至少一个第二区域与所述单元区域区域相对并且具有小于所述至少第一区域的横向尺寸。

公开(公告)号：US08878234B2

公开(公告)日：2014-11-04

申请号：US13781786

申请日：2013-03-01

申请人： Infineon Technologies AG

发明人： Harald Gossner ,  Ramgopal Rao ,  Angada Sachid ,  Ashish Pal ,  Ram Asra

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/739 ,  H01L29/165 ,  H01L21/265 ,  H01L29/06

CPC分类号： H01L29/165 ,  H01L21/26586 ,  H01L29/0657 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/66356 ,  H01L29/7391

摘要： In an embodiment, a semiconductor device is provided. The semiconductor device may include a substrate having a main processing surface, a first source/drain region comprising a first material of a first conductivity type, a second source/drain region comprising a second material of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, a body region electrically coupled between the first source/drain region and the second source/drain region, wherein the body region extends deeper into the substrate than the first source/drain region in a first direction that is perpendicular to the main processing surface of the substrate, a gate dielectric disposed over the body region, and a gate region disposed over the gate dielectric, wherein the gate region overlaps with at least a part of the first source/drain region and with a part of the body region in the first direction.

摘要翻译： 在一个实施例中，提供了半导体器件。 半导体器件可以包括具有主处理表面的衬底，包括第一导电类型的第一材料的第一源极/漏极区域，包括第二导电类型的第二材料的第二源极/漏极区域，其中第二导电类型 不同于第一导电类型，电耦合在第一源极/漏极区域和第二源极/漏极区域之间的主体区域，其中主体区域在第一方向上比第一源极/漏极区域更深地延伸到衬底中 垂直于衬底的主处理表面，设置在主体区域上的栅极电介质和设置在栅极电介质上的栅极区域，其中栅极区域与第一源极/漏极区域的至少一部分重叠， 的身体区域在第一个方向。

公开(公告)号：US20130181256A1

公开(公告)日：2013-07-18

申请号：US13781786

申请日：2013-03-01

申请人： Infineon Technologies AG

发明人： Harald Gossner ,  Ramgopal Rao ,  Angada Sachid ,  Ashish Pal ,  Ram Asra

IPC分类号： H01L29/165

CPC分类号： H01L29/165 ,  H01L21/26586 ,  H01L29/0657 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/66356 ,  H01L29/7391

摘要： In an embodiment, a semiconductor device is provided. The semiconductor device may include a substrate having a main processing surface, a first source/drain region comprising a first material of a first conductivity type, a second source/drain region comprising a second material of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, a body region electrically coupled between the first source/drain region and the second source/drain region, wherein the body region extends deeper into the substrate than the first source/drain region in a first direction that is perpendicular to the main processing surface of the substrate, a gate dielectric disposed over the body region, and a gate region disposed over the gate dielectric, wherein the gate region overlaps with at least a part of the first source/drain region and with a part of the body region in the first direction.

摘要翻译： 在一个实施例中，提供了半导体器件。 半导体器件可以包括具有主处理表面的衬底，包括第一导电类型的第一材料的第一源极/漏极区域，包括第二导电类型的第二材料的第二源极/漏极区域，其中第二导电类型 不同于第一导电类型，电耦合在第一源极/漏极区域和第二源极/漏极区域之间的主体区域，其中主体区域在第一方向上比第一源极/漏极区域在第一方向 垂直于基板的主处理表面，设置在主体区域上的栅极电介质和设置在栅极电介质上的栅极区域，其中栅极区域与第一源极/漏极区域的至少一部分重叠， 的身体区域在第一个方向。

公开(公告)号：US20120228700A1

公开(公告)日：2012-09-13

申请号：US13237309

申请日：2011-09-20

申请人： Akito Nishii ,  Katsumi Nakamura

发明人： Akito Nishii ,  Katsumi Nakamura

IPC分类号： H01L29/78 ,  H01L21/20

CPC分类号： H01L29/861 ,  H01L29/0615 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/423 ,  H01L29/66348 ,  H01L29/7397

摘要： A semiconductor device includes: an N-type drift layer; a P-type anode layer on the N-type drift layer; a trench penetrating the P-type anode layer; a conductive substance embedded in the trench via an insulating film; and an N-type buffer layer between the N-type drift layer and the P-type anode layer and having impurity concentration which is higher than that of the N-type drift layer.

摘要翻译： 一种半导体器件包括：N型漂移层; N型漂移层上的P型阳极层; 穿透P型阳极层的沟槽; 通过绝缘膜嵌入沟槽中的导电物质; 以及在N型漂移层和P型阳极层之间的N型缓冲层，其杂质浓度高于N型漂移层的杂质浓度。