公开(公告)号：US08470705B2

公开(公告)日：2013-06-25

申请号：US13406385

申请日：2012-02-27

Applicant: Wu-Te Weng ,  Ji-Shyang Nieh

Inventor： Wu-Te Weng ,  Ji-Shyang Nieh

IPC: H01L21/44

CPC classification number: H01L23/481 ,  H01L21/76838 ,  H01L23/48 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02122 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/451 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00012 ,  H01L2224/48 ,  H01L2924/00

Abstract: A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in forming the chip pad structure, electrical connections from the gate electrodes of MOS transistors in the IC substrate generally are made only to the ring pad portion that has an antenna-to-gate area ratio substantially below a predetermined antenna design rule ratio, and thus is resistant or immune to antenna effect. The main pad portion and the ring pad portion are coupled together through metal bridges formed in an upper interconnect metal layer or in the top conductive pad layer. The chip pad may be used as probe pads on a parametric testline or bonding pads on an IC.

Abstract translation: 公开了一种集成电路（IC）的芯片焊盘结构及其形成方法。 芯片焊盘包括主焊盘部分和环形焊盘部分。 在形成芯片焊盘结构的充电过程中，IC衬底中的MOS晶体管的栅电极的电连接通常仅由天线到栅极面积比大大低于预定天线设计的环形焊盘部分 规则比例，因此是抗天线效应或免疫天线效应。 主焊盘部分和环形焊盘部分通过形成在上互连金属层或顶部导电焊盘层中的金属桥耦合在一起。 芯片焊盘可用作参数测试线上的探针焊盘或IC上的焊盘。

公开(公告)号：US20120091567A1

公开(公告)日：2012-04-19

申请号：US13334556

申请日：2011-12-22

Applicant: Reza A. Pagaila ,  Byung Tai Do ,  Shuangwu Huang ,  Nathapong Suthiwongsunthorn ,  Dioscoro Merilo

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Shuangwu Huang ,  Nathapong Suthiwongsunthorn ,  Dioscoro Merilo

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/48 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68336 ,  H01L2224/02122 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08145 ,  H01L2224/48 ,  H01L2224/96 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor wafer has a plurality of semiconductor die. A peripheral region is formed around the die. An insulating material is formed in the peripheral region. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. A conductive layer is formed between the conductive THV and contact pads of the semiconductor die. A noise absorbing material is deposited in the peripheral region between the conductive THV to isolate the semiconductor die from intra-device interference. The noise absorbing material extends through the peripheral region from a first side of the semiconductor die to a second side of the semiconductor die. The noise absorbing material has an angular, semi-circular, or rectangular shape. The noise absorbing material can be dispersed in the peripheral region between the conductive THV.

Abstract translation: 半导体晶片具有多个半导体管芯。 围绕模具形成周边区域。 在周边区域形成绝缘材料。 绝缘材料的一部分被去除以形成通孔（THV）。 导电材料沉积在THV中以形成导电THV。 在导电THV和半导体管芯的接触焊盘之间形成导电层。 噪声吸收材料沉积在导电THV之间的周边区域中，以将半导体管芯与器件间干扰隔离。 噪声吸收材料从半导体管芯的第一侧延伸穿过周边区域到半导体管芯的第二侧。 噪声吸收材料具有角度，半圆形或矩形形状。 噪声吸收材料可以分散在导电THV之间的周边区域。

公开(公告)号：US08148797B2

公开(公告)日：2012-04-03

申请号：US11818978

申请日：2008-06-26

Applicant: Wu-Te Weng ,  Ji-Shyang Nieh

Inventor： Wu-Te Weng ,  Ji-Shyang Nieh

IPC: H01L23/52

CPC classification number: H01L23/481 ,  H01L21/76838 ,  H01L23/48 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02122 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/451 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00012 ,  H01L2224/48 ,  H01L2924/00

Abstract: A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in forming the chip pad structure, electrical connections from the gate electrodes of MOS transistors in the IC substrate generally are made only to the ring pad portion that has an antenna-to-gate area ratio substantially below a predetermined antenna design rule ratio, and thus is resistant or immune to antenna effect. The main pad portion and the ring pad portion are coupled together through metal bridges formed in an upper interconnect metal layer or in the top conductive pad layer. The chip pad may be used as probe pads on a parametric testline or bonding pads on an IC.

Abstract translation: 公开了一种集成电路（IC）的芯片焊盘结构及其形成方法。 芯片焊盘包括主焊盘部分和环形焊盘部分。 在形成芯片焊盘结构的充电过程中，IC衬底中的MOS晶体管的栅电极的电连接通常仅由天线到栅极面积比大大低于预定天线设计的环形焊盘部分 规则比例，因此是抗天线效应或免疫天线效应。 主焊盘部分和环形焊盘部分通过形成在上互连金属层或顶部导电焊盘层中的金属桥耦合在一起。 芯片焊盘可用作参数测试线上的探针焊盘或IC上的焊盘。

公开(公告)号：US20100230822A1

公开(公告)日：2010-09-16

申请号：US12404069

申请日：2009-03-13

Applicant: Reza A. Pagaila ,  Byung Tai Do ,  Shuangwu Huang ,  Nathapong Suthiwongsunthorn ,  Dioscoro Merilo

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Shuangwu Huang ,  Nathapong Suthiwongsunthorn ,  Dioscoro Merilo

IPC: H01L23/48 ,  H01L21/50 ,  H01L21/768

CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/48 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68336 ,  H01L2224/02122 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08145 ,  H01L2224/48 ,  H01L2224/96 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor wafer has a plurality of semiconductor die. A peripheral region is formed around the die. An insulating material is formed in the peripheral region. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. A conductive layer is formed between the conductive THV and contact pads of the semiconductor die. A noise absorbing material is deposited in the peripheral region between the conductive THV to isolate the semiconductor die from intra-device interference. The noise absorbing material extends through the peripheral region from a first side of the semiconductor die to a second side of the semiconductor die. The noise absorbing material has an angular, semi-circular, or rectangular shape. The noise absorbing material can be dispersed in the peripheral region between the conductive THV.

Abstract translation: 半导体晶片具有多个半导体管芯。 围绕模具形成周边区域。 在周边区域形成绝缘材料。 绝缘材料的一部分被去除以形成通孔（THV）。 导电材料沉积在THV中以形成导电THV。 在导电THV和半导体管芯的接触焊盘之间形成导电层。 噪声吸收材料沉积在导电THV之间的周边区域中，以将半导体管芯与器件间干扰隔离。 噪声吸收材料从半导体管芯的第一侧延伸穿过周边区域到半导体管芯的第二侧。 噪声吸收材料具有角度，半圆形或矩形形状。 噪声吸收材料可以分散在导电THV之间的周边区域。

公开(公告)号：US07501708B2

公开(公告)日：2009-03-10

申请号：US11461148

申请日：2006-07-31

Applicant: Paul Stephen Andry ,  Steven Lorenz Wright

Inventor： Paul Stephen Andry ,  Steven Lorenz Wright

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/05 ,  H01L23/585 ,  H01L24/12 ,  H01L24/16 ,  H01L2224/02122 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The invention broadly and generally provides a connection structure for connecting a microelectronic device to a substrate, the aforesaid connection structure comprising: (a) a metal layer electrically connected to the aforesaid microelectronic device; (b) an interface element attached to an interface portion of the aforesaid metal layer; (c) a metallic solder element attached to the aforesaid interface element at an interface region of the aforesaid metallic solder element; and (d) a current dispersing structure operable to spatially disperse an electric current, the aforesaid current dispersing structure comprising an electrically insulating material and being disposed within at least one of the aforesaid interface portion, the aforesaid interface element, and the aforesaid interface region.

Abstract translation: 本发明广泛地并且通常提供用于将微电子器件连接到衬底的连接结构，上述连接结构包括：（a）与上述微电子器件电连接的金属层; （b）连接到上述金属层的界面部分的界面元件; （c）在上述金属焊料元件的界面区域附着于上述界面元件的金属焊料元件; 和（d）可操作以空间分散电流的电流分散结构，上述电流分散结构包括电绝缘材料，并且设置在上述界面部分，上述界面元件和上述界面区域中的至少一个内。

公开(公告)号：US20080023851A1

公开(公告)日：2008-01-31

申请号：US11461148

申请日：2006-07-31

Applicant: Paul Stephen Andry ,  Steven Lorenz Wright

Inventor： Paul Stephen Andry ,  Steven Lorenz Wright

IPC: H01L23/48

CPC classification number: H01L24/05 ,  H01L23/585 ,  H01L24/12 ,  H01L24/16 ,  H01L2224/02122 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The invention broadly and generally provides a connection structure for connecting a microelectronic device to a substrate, the aforesaid connection structure comprising: (a) a metal layer electrically connected to the aforesaid microelectronic device; (b) an interface element attached to an interface portion of the aforesaid metal layer; (c) a metallic solder element attached to the aforesaid interface element at an interface region of the aforesaid metallic solder element; and (d) a current dispersing structure operable to spatially disperse an electric current, the aforesaid current dispersing structure comprising an electrically insulating material and being disposed within at least one of the aforesaid interface portion, the aforesaid interface element, and the aforesaid interface region.

Abstract translation: 本发明广泛地并且通常提供用于将微电子器件连接到衬底的连接结构，上述连接结构包括：（a）与上述微电子器件电连接的金属层; （b）连接到上述金属层的界面部分的界面元件; （c）在上述金属焊料元件的界面区域附着于上述界面元件的金属焊料元件; 和（d）可操作以空间分散电流的电流分散结构，上述电流分散结构包括电绝缘材料，并且设置在上述界面部分，上述界面元件和上述界面区域中的至少一个内。

公开(公告)号：US20010010408A1

公开(公告)日：2001-08-02

申请号：US09818455

申请日：2001-03-27

Inventor： Ming-Dou Ker ,  Hsin-Chin Jiang

IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: H01L24/05 ,  H01L23/5222 ,  H01L24/48 ,  H01L2224/02122 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05599 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A low-capacitance bonding pad for a semiconductor device. A diffusion region is formed in a substrate, and a bonding pad is formed on the substrate and aligned with the diffusion region. The bonding pad is made from a stacked metal layer and a metal layer. The stacked metal layer is made from a plurality of metal layers and a plurality of dielectric layers, and the metal layers and the dielectric layers are stacked alternately. The metal layers stacked in the stacked metal layer are formed with small areas. Each of the metal layers stacked in the stacked metal layer is coupled with the adjacent metal layer by via plugs.

公开(公告)号：US20010010407A1

公开(公告)日：2001-08-02

申请号：US09818449

申请日：2001-03-27

Inventor： Ming-Dou Ker ,  Hsin-Chin Jiang

IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: H01L24/05 ,  H01L23/5222 ,  H01L24/48 ,  H01L2224/02122 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05599 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A low-capacitance bonding pad for a semiconductor device. A diffusion region is formed in a substrate, and a bonding pad is formed on the substrate and aligned with the diffusion region. The bonding pad is made from a stacked metal layer and a metal layer. The stacked metal layer is made from a plurality of metal layers and a plurality of dielectric layers, and the metal layers and the dielectric layers are stacked alternately. The metal layers stacked in the stacked metal layer are formed with small areas. Each of the metal layers stacked in the stacked metal layer is coupled with the adjacent metal layer by via plugs.

Abstract translation: 一种用于半导体器件的低电容焊盘。 在衬底中形成扩散区，并且在衬底上形成接合焊盘并与扩散区对准。 接合焊盘由堆叠的金属层和金属层制成。 堆叠的金属层由多个金属层和多个电介质层制成，并且金属层和电介质层交替堆叠。 堆叠在层叠金属层中的金属层形成有小面积。 堆叠在堆叠金属层中的每个金属层通过插塞与相邻的金属层耦合。

公开(公告)号：US5886414A

公开(公告)日：1999-03-23

申请号：US717411

申请日：1996-09-20

Applicant: Terry R. Galloway

Inventor： Terry R. Galloway

IPC: H01L23/58 ,  H01L23/48 ,  H01L23/485 ,  H01L29/54

CPC classification number: H01L22/32 ,  H01L24/05 ,  H01L2224/02122 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/05552 ,  H01L2224/48463 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014

Abstract: Removable extension areas electrically connected to the original die bond pad allow for testing connections to be made. After removal of the extension areas, the circuitry below the region of the extension areas can be seen through a microscope. The use of perforations and/or underlayer sections can aid in the removal of the extension areas. Underlayer sections may comprise a metal that forms an intermetallic interaction with the metal layer of the extension areas.

Abstract translation: 电连接到原始管芯接合焊盘的可移动扩展区允许测试连接。 在移除延伸区域之后，通过显微镜可以看到扩展区域以下的电路。 穿孔和/或下层部分的使用可以帮助移除延伸区域。 底层部分可以包括与扩展区域的金属层形成金属间相互作用的金属。