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    Monitoring Plasma Induced Damage During Semiconductor Wafer Processes
    5.
    发明申请
    Monitoring Plasma Induced Damage During Semiconductor Wafer Processes 有权
    在半导体晶片工艺期间监测等离子体引起的损伤

    公开(公告)号：US20090281745A1

    公开(公告)日：2009-11-12

    申请号：US12433488

    申请日：2009-04-30

    Applicant: Wu Der Weng ,  Ji-Shyang Nieh

    Inventor： Wu Der Weng ,  Ji-Shyang Nieh

    IPC: G01R19/00 ,  H01L23/00 ,  G06F19/00

    CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A plasma damage detection test structure is disclosed. The plasma damage detection test structure includes a first antenna, a voltage source, a ground reference, a first transistor comprising a first source, a first gate, and a first drain. The plasma damage detection test structure further includes a second transistor comprising a second source, a second gate, and a second drain. The first gate is conductively coupled to said first antenna, said first drain and said second drain are conductively coupled to said voltage source, and said first source and said second source are conductively coupled to said ground reference. In various embodiments multiple antennas may be used. The antennas may be multiple configurations, such as a symmetric arrangement or asymmetric arrangement. In various embodiments, multiple transistors in parallel or cross-couple arrangements may be used.

    Abstract translation: 公开了一种等离子体损伤检测测试结构。 等离子体损伤检测测试结构包括第一天线，电压源，接地基准，包括第一源，第一栅极和第一漏极的第一晶体管。 等离子体损伤检测测试结构还包括第二晶体管，其包括第二源极，第二栅极和第二漏极。 第一栅极导电地耦合到所述第一天线，所述第一漏极和所述第二漏极导电耦合到所述电压源，并且所述第一源极和所述第二源极导电地耦合到所述接地基准。 在各种实施例中，可以使用多个天线。 天线可以是多种配置，例如对称布置或非对称布置。 在各种实施例中，可以使用并联或交叉耦合布置的多个晶体管。

    Monitoring plasma induced damage during semiconductor wafer processes
    6.
    发明授权
    Monitoring plasma induced damage during semiconductor wafer processes 有权
    在半导体晶圆工艺期间监测等离子体引起的

    公开(公告)号：US08193824B2

    公开(公告)日：2012-06-05

    申请号：US12433488

    申请日：2009-04-30

    Applicant: Wu-Der Weng ,  Ji-Shyang Nieh

    Inventor： Wu-Der Weng ,  Ji-Shyang Nieh

    IPC: G01R31/00 ,  G01R31/26

    CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A plasma damage detection test structure is disclosed. The plasma damage detection test structure includes a first antenna, a voltage source, a ground reference, a first transistor comprising a first source, a first gate, and a first drain. The plasma damage detection test structure further includes a second transistor comprising a second source, a second gate, and a second drain. The first gate is conductively coupled to said first antenna, said first drain and said second drain are conductively coupled to said voltage source, and said first source and said second source are conductively coupled to said ground reference. In various embodiments multiple antennas may be used. The antennas may be multiple configurations, such as a symmetric arrangement or asymmetric arrangement. In various embodiments, multiple transistors in parallel or cross-couple arrangements may be used.

    Abstract translation: 公开了一种等离子体损伤检测测试结构。 等离子体损伤检测测试结构包括第一天线，电压源，接地基准，包括第一源，第一栅极和第一漏极的第一晶体管。 等离子体损伤检测测试结构还包括第二晶体管，其包括第二源极，第二栅极和第二漏极。 第一栅极导电地耦合到所述第一天线，所述第一漏极和所述第二漏极导电耦合到所述电压源，并且所述第一源极和所述第二源极导电地耦合到所述接地基准。 在各种实施例中，可以使用多个天线。 天线可以是多种配置，例如对称布置或非对称布置。 在各种实施例中，可以使用并联或交叉耦合布置的多个晶体管。

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