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158 条记录 (耗时 0.02 秒)

    Methods of fabricating integrated optoelectronic devices
    51.
    发明授权
    Methods of fabricating integrated optoelectronic devices 有权
    集成光电子器件的制造方法

    公开(公告)号：US07306959B2

    公开(公告)日：2007-12-11

    申请号：US11022364

    申请日：2004-12-22

    申请人： Yue Liu

    发明人： Yue Liu

    IPC分类号： H01L21/00

    CPC分类号： H01L33/486 ,  H01L31/0203 ,  H01L2924/0002 ,  H01S5/0224 ,  H01S5/02272 ,  H01S5/18388 ,  H01L2924/00

    摘要： This disclosure concerns methods for fabrication of integrated high speed optoelectronic devices. In one example of such a method, a device region that includes a top surface and a bottom surface is formed on a top surface of a substrate. The device region may take the form of an optical emitter, such as a VCSEL, or a detector, such as a photodiode. Next, an isolation region is formed that is configured such that the device region is surrounded by the isolation region. A superstrate is then disposed on the top surface of the device region. Finally, a micro-optical device, such as a lens, is placed on a top surface of the superstrate.

    摘要翻译： 本公开涉及用于制造集成高速光电子器件的方法。 在这种方法的一个实例中，包括顶表面和底表面的器件区域形成在衬底的顶表面上。 器件区域可以采取诸如VCSEL的光发射器或诸如光电二极管的检测器的形式。 接下来，形成隔离区域，其被配置为使得器件区域被隔离区域包围。 然后在装置区域的顶表面上设置覆盖层。 最后，诸如透镜的微光学装置被放置在顶板的顶表面上。

    Protective side wall passivation for VCSEL chips
    54.
    发明授权
    Protective side wall passivation for VCSEL chips 失效
    VCSEL芯片的保护侧壁钝化

    公开(公告)号：US06924161B2

    公开(公告)日：2005-08-02

    申请号：US10427237

    申请日：2003-05-01

    申请人： James C. Nohava ,  Robert A. Morgan ,  Eva M. B. Strzelecka ,  Yue Liu

    发明人： James C. Nohava ,  Robert A. Morgan ,  Eva M. B. Strzelecka ,  Yue Liu

    IPC分类号： H01L29/06 ,  H01S5/183 ,  H01L21/00

    CPC分类号： H01S5/18313 ,  H01S5/0202 ,  H01S2301/176

    摘要： Methods for sealing or passivating the edges of chips such as vertical cavity surface emitting lasers (VCSEL) is disclosed. One method includes oxidizing the edges of die at the wafer level prior to cutting the wafer into a plurality of die. This may be accomplished by etching a channel along the streets between die, followed by oxidizing the channel walls. The oxidation preferably oxidizes the aluminum bearing layers that are exposed by the channel walls inward for distance. Aluminum bearing layers, including AlAs and AlGaAs, may be oxidized to a stable native oxide that is resistant to further oxidation by the environment. After oxidation, the wafer can be cut along the channels into a number of die, each having a protective oxide layer on the side surfaces.

    摘要翻译： 公开了用于密封或钝化诸如垂直腔表面发射激光器（VCSEL）的芯片的边缘的方法。 一种方法包括在将晶片切割成多个管芯之前，在晶片级处氧化管芯的边缘。 这可以通过沿模具之间的街道蚀刻通道，然后氧化通道壁来实现。 氧化优选氧化由通道壁向内暴露的距离的含铝层。 包括AlAs和AlGaAs的铝轴承层可以被氧化成稳定的天然氧化物，其耐受环境的进一步氧化。 氧化后，可以将晶片沿着通道切割成多个模具，每个模具在侧表面上具有保护性氧化物层。

    Integration of top-emitting and top-illuminated optoelectronic devices with micro-optic and electronic integrated circuits
    55.
    发明授权
    Integration of top-emitting and top-illuminated optoelectronic devices with micro-optic and electronic integrated circuits 失效
    顶部发光和顶部照明光电子器件与微光学和电子集成电路的集成

    公开(公告)号：US06780661B1

    公开(公告)日：2004-08-24

    申请号：US09547538

    申请日：2000-04-12

    申请人： Yue Liu

    发明人： Yue Liu

    IPC分类号： H01L2100

    CPC分类号： H01S5/0262 ,  H01S5/0207 ,  H01S5/0213 ,  H01S5/0215 ,  H01S5/0216 ,  H01S5/02272 ,  H01S5/18388

    摘要： An opto-electronic integrated circuit device includes top emitter/detector devices on a substrate. The top emitter/detector devices have top and bottom sides. The top emitter/detector devices are capable of emitting and detecting light beam from the top side, and have top contact pads on the top side. An optically transparent superstrate is attached to the top side. Micro-optic devices such as lenses can be attached to the superstrate. Top contact pads are connected to bottom contact pads. The bottom contact pads are attached to matching pads of an integrated circuit chip to produce an opto-electronic integrated circuit.

    摘要翻译： 光电集成电路器件包括衬底上的顶部发射器/检测器器件。 顶部发射器/检测器装置具有顶部和底部。 顶部发射器/检测器装置能够发射和检测来自顶侧的光束，并且在顶侧具有顶部接触焊盘。 光学透明的上层附着在顶面。 诸如透镜的微光学装置可以附着在上面。 顶部接触垫连接到底部接触垫。 底部接触焊盘连接到集成电路芯片的匹配焊盘以产生光电集成电路。

    Method for Producing High Stacking Fault Energy (SFE) Metal Films, Foils, and Coatings with High-Density Nanoscale Twin Boundaries
    58.
    发明申请
    Method for Producing High Stacking Fault Energy (SFE) Metal Films, Foils, and Coatings with High-Density Nanoscale Twin Boundaries 有权
    高密度纳米尺度双边界产生高堆叠断层能量（SFE）金属膜，箔片和涂层的方法

    公开(公告)号：US20150233019A1

    公开(公告)日：2015-08-20

    申请号：US14428538

    申请日：2013-09-17

    申请人： Xinghang ZHANG ,  Daniel BUFFORD ,  Haiyon WANG ,  Yue LIU

    发明人： Xinghang Zhang ,  Daniel Bufford ,  Haiyan Wang ,  Yue Liu

    IPC分类号： C30B29/68 ,  C30B29/02

    CPC分类号： C30B29/68 ,  C23C14/165 ,  C30B23/025 ,  C30B29/02 ,  Y10T428/12472

    摘要： Materials, including metals such as bulk metals, specialty alloys, metallic films and coatings, are made up of many tiny single crystals, which may also be referred to as grains. The boundaries between crystals are called grain boundaries and govern properties such as mechanical strength, deformation, and electrical resistivity. These properties are affected by not only the number of grain boundaries formed, but also the density and orientation of those grain boundaries. Twin boundaries are a special type of grain boundary which have symmetrical “mirror image” structures and preserve favorable qualities of grain boundaries while suppressing unfavorable properties such as the initiation of cracks, inclusions, and other unwanted flaws. Some metals and alloys form twins more easily than others during processing. Metals with low stacking fault energy (SFE) such as austenitic stainless steel, copper (Cu), and silver (Ag) form twin boundaries more easily than metals with high SFE such as Magnesium (Mg) and Aluminum (Al).

    摘要翻译： 包括诸如散装金属，特种合金，金属膜和涂层的金属的材料由许多微小的单晶组成，其也可以称为晶粒。 晶体之间的边界称为晶界和管理性质，如机械强度，变形和电阻率。 这些性质不仅受到形成的晶粒数量的影响，还受到这些晶界的密度和取向的影响。 双边界是具有对称“镜像”结构的特殊类型的晶界，并且在抑制裂纹，夹杂物等不希望的缺陷的不利特性的同时保持晶界的有利品质。 一些金属和合金在加工过程中比其他金属和合金更容易形成双胞胎。 具有低堆垛层错能量（SFE）的金属如奥氏体不锈钢，铜（Cu）和银（Ag）比具有高SFE的金属如镁（Mg）和铝（Al）更容易形成双边界。

    Method of forming a spin valve structure with a composite spacer in a magnetic read head
    60.
    发明授权
    Method of forming a spin valve structure with a composite spacer in a magnetic read head 有权
    在磁读头中用复合间隔物形成自旋阀结构的方法

    公开(公告)号：US08978240B2

    公开(公告)日：2015-03-17

    申请号：US13200013

    申请日：2011-09-15

    申请人： Kunliang Zhang ,  Min Li ,  Moris Dovek ,  Yue Liu

    发明人： Kunliang Zhang ,  Min Li ,  Moris Dovek ,  Yue Liu

    IPC分类号： G11B5/127 ,  H04R31/00 ,  G11B5/39 ,  B82Y10/00 ,  B82Y25/00

    CPC分类号： G11B5/3909 ,  B82Y10/00 ,  B82Y25/00 ,  G11B5/3906 ,  G11B2005/3996 ,  Y10T29/49039 ,  Y10T29/49043 ,  Y10T29/49044

    摘要： A CPP-GMR spin valve having a composite spacer layer comprised of at least one metal (M) layer and at least one semiconductor or semi-metal (S) layer is disclosed. The composite spacer may have a M/S, S/M, M/S/M, S/M/S, M/S/M/S/M, or a multilayer (M/S/M)n configuration where n is an integer≧1. The pinned layer preferably has an AP2/coupling/AP1 configuration wherein the AP2 portion is a FCC trilayer represented by CoZFe(100-Z)/FeYCo(100-Y)/CoZFe(100-Z) where y is 0 to 60 atomic %, and z is 75 to 100 atomic %. In one embodiment, M is Cu with a thickness from 0.5 to 50 Angstroms and S is ZnO with a thickness of 1 to 50 Angstroms. The S layer may be doped with one or more elements. The dR/R ratio of the spin valve is increased to 10% or greater while maintaining acceptable EM and RA performance.

    摘要翻译： 公开了具有由至少一个金属（M）层和至少一个半导体或半金属（S）层组成的复合间隔层的CPP-GMR自旋阀。 复合间隔物可以具有M / S，S / M，M / S / M，S / M / S，M / S / M / S / M或多层（M / S / M） 是整数≧1。 钉扎层优选具有AP2 /耦合/ AP1配置，其中AP2部分是由CoZFe（100-Z）/ FeYCo（100-Y）/ CoZFe（100-Z）表示的FCC三层，其中y为0至60原子％ ，z为75〜100原子％。 在一个实施方案中，M是厚度为0.5至50埃的Cu，S是厚度为1至50埃的ZnO。 S层可以掺杂有一个或多个元素。 自旋阀的dR / R比提高到10％以上，同时保持可接受的EM和RA性能。