公开(公告)号：US20230155002A1

公开(公告)日：2023-05-18

申请号：US17700998

申请日：2022-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hang Chiu ,  Wei-Cheng Wang ,  Chung-Chiang Wu ,  Chi On Chui

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/0259 ,  H01L21/28088 ,  H01L29/0665 ,  H01L29/4908 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

Abstract: Embodiments provide a replacement metal gate in a FinFET or nanoFET which utilizes a conductive metal fill. The conductive metal fill has an upper surface which has a fin shape which may be used for a self-aligned contact.

公开(公告)号：US20230140968A1

公开(公告)日：2023-05-11

申请号：US18154087

申请日：2023-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hang Chiu ,  Chung-Chiang Wu ,  Jo-Chun Hung ,  Wei-Cheng Wang ,  Kuan-Ting Liu ,  Chi On Chui

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/28

CPC classification number: H01L29/4908 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/02603 ,  H01L29/66742 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/66553 ,  H01L29/66545 ,  H01L21/28088

Abstract: Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.

公开(公告)号：US20230126442A1

公开(公告)日：2023-04-27

申请号：US17662532

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Ju Chen ,  Shu-Han Chen ,  Chun-Heng Chen ,  Chi On Chui

IPC: H01L29/66

Abstract: A method includes forming a dummy gate oxide on a wafer, and the dummy gate oxide is formed on a sidewall and a top surface of a protruding semiconductor fin in the wafer. The formation of the dummy gate oxide may include a Plasma Enhanced Chemical Vapor Deposition (PECVD) process in a deposition chamber, and the PECVD process includes applying a Radio Frequency (RF) power to a conductive plate below the wafer. The method further includes forming a dummy gate electrode over the dummy gate oxide, removing the dummy gate electrode and the dummy gate oxide to form a trench between opposing gate spacers, and forming a replacement gate in the trench.

公开(公告)号：US20230066477A1

公开(公告)日：2023-03-02

申请号：US17462233

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/51 ,  H01L29/40

Abstract: Embodiments include a device and method of forming a device, such as a nano-FET transistor, including a first nanostructure. A gate dielectric is formed around the first nanostructure. A gate electrode is formed over the gate dielectric, and the gate electrode includes a first work function metal. In the gate electrode, a first metal residue is formed at an interface between the gate dielectric and the first work function metal as a result of a treatment process performed prior to forming the first work function metal. The first metal residue has a metal element that is different than a metal element of the first work function metal.

公开(公告)号：US11594633B2

公开(公告)日：2023-02-28

申请号：US17328145

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Chi On Chui ,  Huang-Lin Chao

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02

Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

公开(公告)号：US20230020099A1

公开(公告)日：2023-01-19

申请号：US17648152

申请日：2022-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui ,  Chun-I Wu ,  Huang-Lin Chao

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/49 ,  H01L21/285 ,  H01L21/28

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, depositing a metal-containing layer over the gate dielectric layer, and depositing a silicon-containing layer on the metal-containing layer. The metal-containing layer and the silicon-containing layer in combination act as a work-function layer. A planarization process is performed to remove excess portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer, with remaining portions of the silicon-containing layer, the silicon-containing layer, and the gate dielectric layer forming a gate stack.

公开(公告)号：US20220406784A1

公开(公告)日：2022-12-22

申请号：US17668770

申请日：2022-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Yu ,  Bo-Feng Young ,  Hung Wei Li ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L27/108 ,  H01L29/10

Abstract: Embodiments of the present disclosure provide a side-channel dynamic random access memory (DRAM) cell and cell array that utilizes a vertical design with side channel transistors. A dielectric layer disposed over a substrate. A gate electrode is embedded in the dielectric layer. A channel layer wraps the gate electrode and a conductive structure is adjacent to the channel layer, with the channel layer interposed between the gate electrode and the conductive structure. The semiconductor structure also includes a dielectric structure disposed over the conductive structure and the gate electrode, the channel layer extending up through the dielectric structure.

公开(公告)号：US11527542B2

公开(公告)日：2022-12-13

申请号：US16904717

申请日：2020-06-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Chi On Chui ,  Chenchen Jacob Wang

IPC: H01L27/11509 ,  H01L49/02 ,  H01L27/11507 ,  H01L27/11502 ,  H01L27/108

Abstract: A semiconductor device includes: a substrate; a first dielectric layer over the substrate; a memory cell over the substrate in a first region of the semiconductor device, where the memory cell includes a first ferroelectric structure in the first dielectric layer, where the first ferroelectric structure includes a first bottom electrode, a first top electrode, and a first ferroelectric layer in between; and a tunable capacitor over the substrate in a second region of the semiconductor device, where the tunable capacitor includes a second ferroelectric structure, where the second ferroelectric structure includes a second bottom electrode, a second top electrode, and a second ferroelectric layer in between, where at least a portion of the second ferroelectric structure is in the first dielectric layer.

公开(公告)号：US20220384483A1

公开(公告)日：2022-12-01

申请号：US17883834

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chi On Chui ,  Han-Jong Chia ,  Chenchen Jacob Wang

IPC: H01L27/11597 ,  H01L27/1159

Abstract: A method of forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, the first layer stack and the second layer stack having a same layered structure that includes a dielectric material, a channel material over the dielectric material, and a source/drain material over the channel material; forming openings that extend through the first layer stack and the second layer stack; forming inner spacers by replacing portions of the source/drain material exposed by the openings with a first dielectric material; lining sidewalls of the openings with a ferroelectric material; forming gate electrodes by filling the openings with an electrically conductive material; forming a recess through the first layer stack and the second layer stack, the recess extending from a sidewall of the second layer stack toward the gate electrodes; and filling the recess with a second dielectric material.

公开(公告)号：US20220384461A1

公开(公告)日：2022-12-01

申请号：US17884062

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ming Lin ,  Bo-Feng Young ,  Sai-Hooi Yeong ,  Han-Jong Chia ,  Chi On Chui

IPC: H01L27/1159 ,  H01L27/11597 ,  H01L27/11587 ,  G11C8/14

Abstract: A device includes a semiconductor substrate; a first word line over the semiconductor substrate, the first word line providing a first gate electrode for a first transistor; and a second word line over the first word line. The second word line is insulated from the first word line by a first dielectric material, and the second word line providing a second gate electrode for a second transistor over the first transistor. The device further including a source line intersecting the first word line and the second word line; a bit line intersecting the first word line and the second word line; a memory film between the first word line and the source line; and a first semiconductor material between the memory film and the source line.