公开(公告)号：US10600487B2

公开(公告)日：2020-03-24

申请号：US16205334

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Wan Nam ,  Dong-Hun Kwak ,  Chi-Weon Yoon

IPC: G11C16/04 ,  G11C16/16 ,  G11C8/12 ,  H01L27/11573 ,  H01L27/11582 ,  G11C16/14

Abstract: A method of operating a nonvolatile memory device includes erasing data within a NAND string of memory cells within the memory device by applying a non-zero erase voltage to a source/drain terminal at a first end of the NAND string. This erase voltage is applied concurrently with establishing gate-induced drain leakage (GIDL) in a pair of selection transistors within the NAND string. This GIDL can occur by applying unequal and non-zero first and second voltages to respective first and second gate terminals of the pair of selection transistors. The selection transistors can be string selection transistors or ground selection transistors.

公开(公告)号：US10541033B2

公开(公告)日：2020-01-21

申请号：US15911208

申请日：2018-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won-Taeck Jung ,  Sang-Wan Nam ,  Jinwoo Park ,  Jaeyong Jeong

IPC: G11C16/10 ,  G11C16/20 ,  G11C16/08 ,  G11C16/34 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556

Abstract: A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.

公开(公告)号：US10121542B2

公开(公告)日：2018-11-06

申请号：US15681479

申请日：2017-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Wan Nam ,  Daeseok Byeon ,  Chiweon Yoon

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/28 ,  G11C16/26 ,  G11C16/34

Abstract: A nonvolatile memory device includes a memory cell array and a row decoder circuit. The row decoder circuit turns on memory cells of a plurality of cell strings of a selected memory block after applying a first prepulse to a first dummy word line connected to first dummy memory cells after applying a second prepulse to a second dummy word line connected to second dummy memory cells.

公开(公告)号：US10043580B2

公开(公告)日：2018-08-07

申请号：US15790257

申请日：2017-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Wan Nam ,  Won-Taeck Jung

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C16/08 ,  G11C16/24

Abstract: A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ground selection lines while continuing to apply the turn-on voltage to a selected string selection line and a selected ground selection line. In both the first and second intervals, the device applies a first read voltage to a selected wordline connected to memory cells to be read by the read operation and applying a second read voltage to unselected wordlines among connected to memory cells not to be read by the read operation.

公开(公告)号：USRE46887E1

公开(公告)日：2018-06-05

申请号：US14805938

申请日：2015-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： ChiWeon Yoon ,  Donghyuk Chae ,  Sang-Wan Nam ,  Sung-Won Yun

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  H01L29/792 ,  H01L27/11582 ,  H01L29/788 ,  H01L27/11556

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3418 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

Abstract: Non-volatile memory device channel boosting methods in which at least two strings are connected to one bit line, the channel boosting methods including applying an initial channel voltage to channels of strings in a selected memory block, floating inhibit strings each having an un-programmed cell among the strings, and boosting channels of the floated inhibit strings.

公开(公告)号：US09508441B1

公开(公告)日：2016-11-29

申请号：US15131237

申请日：2016-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Wan Nam ,  Dae-Seok Byeon ,  Chi-Weon Yoon

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/08

CPC classification number: G11C16/10 ,  G11C16/0483

Abstract: A memory device includes a memory cell array including a plurality of NAND strings, wherein each of the NAND strings includes a ground selection transistor connected to a ground selection line, memory cells connected to word lines, and a string selection transistor connected to a string selection line, wherein the ground selection line, the word lines, and the string selection line are vertically stacked on a substrate. A control logic adjusts a ground selection line voltage applied to the ground selection line or a string selection line voltage applied to the string selection line to a negative level in at least a portion of a program section during which a program operation related to a memory cell selected from among the memory cells is performed.

Abstract translation: 存储器件包括包括多个NAND串的存储单元阵列，其中每个NAND串包括连接到接地选择线的接地选择晶体管，连接到字线的存储单元和连接到串选择的串选择晶体管 线，其中地面选择线，字线和弦选择线垂直地堆叠在基底上。 控制逻辑在施加到接地选择线的接地选择线电压或施加到串选择线的串选择线电压在程序部分的至少一部分中将与存储器单元相关的程序操作 从存储单元中进行选择。

公开(公告)号：US09496038B1

公开(公告)日：2016-11-15

申请号：US15091843

申请日：2016-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghun Kwak ,  Sang-Wan Nam ,  Daeseok Byeon ,  Chiweon Yoon

IPC: G11C16/04 ,  G11C16/28 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G11C7/14 ,  G11C8/14 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3418

Abstract: A three-dimensional flash memory device includes a plurality of cell strings arranged in a direction perpendicular to a substrate. The three-dimensional flash memory includes a first dummy word line disposed between a ground selection line and a main word line, and a second dummy word line disposed between the main word line and a string selection line and being asymmetric with respect to the first dummy word line. Voltages of different levels are respectively applied to the first and second dummy word lines during a read operation.

Abstract translation: 三维闪速存储器件包括沿垂直于衬底的方向布置的多个单元串。 三维闪存包括设置在地选择线和主字线之间的第一虚拟字线和设置在主字线和字串选择线之间的第二虚拟字线，并且相对于第一伪线不对称 字线。 在读取操作期间，不同电平的电压分别应用于第一和第二伪字线。

公开(公告)号：US09478290B1

公开(公告)日：2016-10-25

申请号：US14938394

申请日：2015-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Wan Nam ,  Kyung-Hwa Kang ,  Dae-Seok Byeon ,  Chi-Weon Yoon

IPC: G11C16/00 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G11C7/14 ,  G11C8/14 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3427 ,  H01L27/11575 ,  H01L27/11582

Abstract: A memory device is provided as follows. A memory cell array includes strings including first and second strings. Each string includes a ground selection transistor and cell transistors. First and second ground selection lines are connected to a gate of a first ground selection transistor of the first string and a gate of a second ground selection transistor of the second string, respectively. First and second cell gate lines are connected to a gate of a first cell transistor of the first string and a gate of a second cell transistor of the second string, respectively. A first interconnection unit electrically connects a first portion of the first cell gate line to a first portion of the second cell gate line. A second interconnection unit electrically connects a second portion of the first cell gate line to a second portion of the second cell gate line.

Abstract translation: 如下提供存储器件。 存储单元阵列包括包括第一和第二串的串。 每个串包括接地选择晶体管和单元晶体管。 第一和第二接地选择线分别连接到第一串的第一接地选择晶体管的栅极和第二串的第二接地选择晶体管的栅极。 第一和第二单元栅极线分别连接到第一串的第一单元晶体管的栅极和第二串的第二单元晶体管的栅极。 第一互连单元将第一单元栅极线的第一部分电连接到第二单元栅极线的第一部分。 第二互连单元将第一单元栅极线的第二部分电连接到第二单元栅极线的第二部分。

公开(公告)号：US09159443B2

公开(公告)日：2015-10-13

申请号：US14052227

申请日：2013-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chi Weon Yoon ,  Donghyuk Chae ,  Jae-Woo Park ,  Sang-Wan Nam

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/04 ,  G11C16/06 ,  G11C16/16

CPC classification number: G11C16/3445 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/16 ,  H01L29/792

Abstract: A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.

Abstract translation: 操作非易失性存储器件的方法包括对与多个串选择线（SSL）相关联的存储器单元执行擦除操作，与构成存储块的多个SSL相关联的存储器单元，以及将擦除操作 在对与第一SSL相关联的第一存储器单元进行擦除操作之后，与第二SSL相关联的第二存储器单元。

公开(公告)号：US08693247B2

公开(公告)日：2014-04-08

申请号：US13919127

申请日：2013-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chi-Weon Yoon ,  Dong-Hyuk Chae ,  Sang-Wan Nam ,  Sung-Won Yun

IPC: G11C16/00 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3418

Abstract: A non-volatile memory device comprises a memory cell array comprising memory cells arranged in rows connected to corresponding word lines and columns connected to corresponding bit lines, a page buffer that stores a program data, a read-write circuit that programs and re-programs the program data into selected memory cells of the memory cell array and reads stored data from the programmed memory cells, and a control circuit that controls the page buffer and the read-write circuit to program the selected memory cells by loaded the program data from in page buffer and to re-program the selected memory cells by re-loaded the program data in the page buffer.

Abstract translation: 一种非易失性存储器件包括存储单元阵列，该存储单元阵列包括连接到相应的字线和连接到相应位线的列的行中的存储单元，存储程序数据的页缓冲器，用于编程和重新编程的读写电路 将程序数据写入到存储单元阵列的选择的存储单元中，并从编程的存储器单元中读取存储的数据;以及控制电路，其控制页面缓冲器和读写电路，以通过从其中加载程序数据对所选存储单元进行编程 页面缓冲区，并通过重新加载页面缓冲区中的程序数据来重新编程所选择的存储单元。