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    INTEGRATED ELECTRONIC DEVICE FOR MONITORING MECHANICAL STRESS WITHIN A SOLID STRUCTURE
    51.
    发明申请
    INTEGRATED ELECTRONIC DEVICE FOR MONITORING MECHANICAL STRESS WITHIN A SOLID STRUCTURE 有权
    用于在固体结构中监测机械应力的集成电子设备

    公开(公告)号：US20140182390A1

    公开(公告)日：2014-07-03

    申请号：US14108951

    申请日：2013-12-17

    Applicant: STMicroelectronics S.r.l.

    Inventor： Alberto PAGANI ,  Federico Giovanni Ziglioli ,  Bruno Murari

    IPC: G01L1/18 ,  H01L27/20

    CPC classification number: G01L1/18 ,  H01L27/20

    Abstract: The integrated electronic device is for detecting a local parameter related to a force observed in a given direction, within a solid structure. The device includes at least one sensor configured to detect the above-mentioned local parameter at least in the given direction through piezo-resistive effect. At least one damping element, integrated in the device, is arranged within a frame-shaped region that is disposed around the at least one sensor and belongs to a substantially planar region comprising a plane passing through the sensor and perpendicular to the given direction. Such at least one damping element is configured to damp forces acting in the planar region and substantially perpendicular to the given direction.

    Abstract translation: 集成电子装置用于在固体结构内检测与在给定方向上观察到的力有关的局部参数。 该装置包括至少一个传感器，其配置成至少在给定方向上通过压阻效应来检测上述局部参数。 集成在装置中的至少一个阻尼元件布置在围绕至少一个传感器设置的框状区域中，并且属于基本上平面的区域，该区域包括通过传感器并垂直于给定方向的平面。 这样的至少一个阻尼元件构造成阻碍作用在平面区域中并基本垂直于给定方向的力。

    Semiconductor package with wettable flank
    52.
    发明授权
    Semiconductor package with wettable flank 有权

    公开(公告)号：US10930581B2

    公开(公告)日：2021-02-23

    申请号：US15159604

    申请日：2016-05-19

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Federico Giovanni Ziglioli

    IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78

    Abstract: Embodiments of the present disclosure are directed to flat no-lead packages with wettable sidewalls or flanks. In particular, wettable conductive layers are formed on the package over lateral portions of the leads and on portions of the package body, which may be encapsulation material. The wettable conductive layers may also be formed on bottom surfaces of the package body and the leads. The wettable conductive layers provide a wettable flank for solder to wick up when the package is mounted to a substrate, such as a PCB, using SMT. In particular, solder that is used to join the PCB and the package wicks up the side of the wettable conductive layers along a side surface of the package. In that regard, the solder is exposed and coupled to the side surface of the package at the wettable conductive layers, thereby allowing for a visual inspection of the solder joints. The wettable conductive layers are formed on the package after the package body has been formed. In one embodiment, the wettable conductive layers are printed on the package body and the leads by Aerosol Jet® technology.

    Tensile stress measurement device with attachment plates and related methods
    56.
    发明授权
    Tensile stress measurement device with attachment plates and related methods 有权

    公开(公告)号：US09726587B2

    公开(公告)日：2017-08-08

    申请号：US14610068

    申请日：2015-01-30

    Applicant: STMICROELECTRONICS S.r.l.

    Inventor： Alberto Pagani ,  Bruno Murari ,  Federico Giovanni Ziglioli

    IPC: G01N3/08 ,  H01L23/31 ,  G01N3/06

    CPC classification number: G01N3/08 ,  G01L1/005 ,  G01N3/066 ,  H01L23/3107

    Abstract: A tensile stress measurement device is to be attached to an object to be measured. The tensile stress measurement device may include an IC having a semiconductor substrate and tensile stress detection circuitry, the semiconductor substrate having opposing first and second attachment areas. The tensile stress measurement device may include a first attachment plate coupled to the first attachment area and extending outwardly to be attached to the object to be measured, and a second attachment plate coupled to the second attachment area and extending outwardly to be attached to the object to be measured. The tensile stress detection circuitry may be configured to detect a tensile stress imparted on the first and second attachment plates when attached to the object to be measured.

    Wafer-level packaging of a MEMS integrated device and related manufacturing process
    59.
    发明授权
    Wafer-level packaging of a MEMS integrated device and related manufacturing process 有权
    MEMS集成器件的晶圆级封装及相关制造工艺

    公开(公告)号：US09187310B2

    公开(公告)日：2015-11-17

    申请号：US14030867

    申请日：2013-09-18

    Applicant: STMicroelectronics S.r.l.

    Inventor： Federico Giovanni Ziglioli

    IPC: B81B3/00 ,  B81B7/00 ,  B81C1/00

    CPC classification number: B81B3/0021 ,  B81B7/007 ,  B81B2207/012 ,  B81B2207/096 ,  B81C1/00269 ,  B81C2203/0118 ,  B81C2203/0792 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/73265 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/00014

    Abstract: A wafer-level package for a MEMS integrated device, envisages: a first body integrating a micromechanical structure; a second body having an active region integrating an electronic circuit, coupled to the micromechanical structure; and a third body defining a covering structure for the first body. The second body defines a base portion of the package and has an inner surface coupled to which is the first body, and an outer surface provided on which are electrical contacts towards the electronic circuit; a routing layer has an inner surface set in contact with the outer surface of the second body and an outer surface that carries electrical contact elements towards the external environment. The third body defines a covering portion for covering the package and is directly coupled to the second body for closing a housing space for the first body.

    Abstract translation: 用于MEMS集成器件的晶片级封装设想：集成微机械结构的第一体; 具有集成电子电路的有源区域的第二主体，耦合到所述微机械结构; 以及限定第一主体的覆盖结构的第三主体。 所述第二主体限定所述包装的基部，并且具有联接到所述第一主体的内表面，并且设置在所述外表面上的电接触朝向所述电子电路的外表面; 路由层具有与第二主体的外表面接触的内表面和将电接触元件朝外部环境承载的外表面。 第三主体限定用于覆盖封装的覆盖部分，并且直接联接到第二主体以封闭用于第一主体的容纳空间。

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