公开(公告)号：US20230354588A1

公开(公告)日：2023-11-02

申请号：US18117604

申请日：2023-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Junhyeok AHN ,  Keunnam KIM ,  Chan-Sic YOON ,  Myeong-Dong LEE

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/02

Abstract: A semiconductor memory device includes a semiconductor substrate; a device isolation layer defining an active portion in the semiconductor substrate; a bit line structure intersecting the active portion on the semiconductor substrate; a first conductive pad between the bit line structure and the active portion; a bit line contact pattern between the first conductive pad and the bit line structure; a first bit line contact spacer covering a first sidewall of the first conductive pad; and a second bit line contact spacer covering a second sidewall of the first conductive pad, wherein the first conductive pad has a flat bottom surface that is in contact with a top surface of the active portion, and a width of the first bit line contact spacer is different from a width of the second bit line contact spacer.

公开(公告)号：US20230320066A1

公开(公告)日：2023-10-05

申请号：US17951379

申请日：2022-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moonyoung JEONG ,  Kiseok LEE ,  Hyungeun CHOI ,  Hyungjun NOH ,  Sangho LEE

IPC: H01L27/108

CPC classification number: H01L27/10805

Abstract: A semiconductor device may include a substrate including a memory cell region between a first connection region and a second connection region, gate electrodes extending in a first direction and including first pad regions having a step structure on the first connection region, back gate electrodes between the gate electrodes and extending in a direction opposite the first direction, vertical conductive patterns extending in a vertical direction and spaced apart from each other in the first direction on the memory cell region of the substrate, and active layers between the gate electrodes and the back gate electrodes on the memory cell region of the substrate. The active layers may extend in a second direction, intersecting the first direction, and may be electrically connected to the vertical conductive patterns. The back gate electrodes may include second pad regions having a step structure on the second connection region.

公开(公告)号：US20230253318A1

公开(公告)日：2023-08-10

申请号：US18062811

申请日：2022-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok LEE ,  Chansic YOON ,  Keunnam KIM

IPC: H01L23/528 ,  H10B12/00

CPC classification number: H01L23/5283 ,  H01L27/10888 ,  H01L27/10891 ,  H01L27/10885 ,  H01L27/10814

Abstract: A semiconductor device includes a substrate including an active region, a word line structure, a bit line structure on the substrate, and a bit line contact pattern configured to electrically connect a first impurity region of the active region with the bit line structure. The device includes a storage node contact on a side wall of the bit line structure, and the storage node contact is electrically connected to a second impurity region of the active region. The device includes a spacer structure on a side wall of the bit line structure, the spacer structure on a side wall of the bit line contact pattern, the spacer structure including a lower spacer structure surrounding a side surface of the lower portion, and an upper spacer structure disposed on a side surface of the upper portion. The device includes a capacitor structure electrically connected to the storage node contact.

公开(公告)号：US20230164980A1

公开(公告)日：2023-05-25

申请号：US17829446

申请日：2022-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeran LEE ,  Kiseok LEE

IPC: H01L27/108 ,  H01L27/22 ,  H01L27/24

CPC classification number: H01L27/10823 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/228 ,  H01L27/2436

Abstract: A semiconductor device includes a substrate including an active portion defined by a device isolation pattern; a word line in the substrate, the word line crossing the active portion and extending in a first direction; a bit line crossing the active portion and the word line and extending in a second direction intersecting the first direction; a first pad on an end portion of the active portion; a first contact on the first pad and adjacent to the bit line in the first direction; and an insulating separation pattern on the word line and adjacent to the first contact in the second direction, wherein the first contact includes a barrier pattern on the first pad, and a conductive pattern vertically extending from the barrier pattern, and a side surface of the conductive pattern of the first contact is in direct contact with the insulating separation pattern.

公开(公告)号：US20230035660A1

公开(公告)日：2023-02-02

申请号：US17683765

申请日：2022-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoin LEE ,  Kiseok LEE

IPC: H01L29/423 ,  H01L29/40

Abstract: A semiconductor device includes lower electrodes, a first supporter structure including first supporter patterns interconnecting the lower electrodes, wherein side surfaces of the first supporter patterns and side surfaces of the lower electrodes that are exposed by the first supporter patterns at least partially define a first open region, the first supporter patterns being spaced apart from one another, the first open region extending among the first supporter patterns in a horizontal direction, a dielectric layer covering the first supporter structure and the lower electrodes, and an upper electrode on the dielectric layer. A distance between adjacent ones of the first supporter patterns is smaller than or equal to a pitch of the lower electrodes.

公开(公告)号：US20220173106A1

公开(公告)日：2022-06-02

申请号：US17369320

申请日：2021-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungeun CHOI ,  Kiseok LEE ,  Seungjae JUNG ,  Joongchan SHIN ,  Taehyun AN ,  Moonyoung JEONG ,  Sangyeon HAN

IPC: H01L27/108 ,  H01L29/08

Abstract: A semiconductor memory device includes: a bit line extending on a substrate in a vertical direction; a transistor body part including a first source-drain region, a monocrystalline channel layer, and a second source-drain region that are sequentially arranged in a first horizontal direction and connected to the bit line; gate electrode layers extending in a second horizontal direction that is orthogonal to the first horizontal direction, with a gate dielectric layer between the gate electrode layers and the monocrystalline channel layer, and covering upper and lower surfaces of the monocrystalline channel layer; and a cell capacitor including a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer at a side of the transistor body that is opposite to the bit line in the first horizontal direction and is connected to the second source-drain region.

公开(公告)号：US20220020758A1

公开(公告)日：2022-01-20

申请号：US17192086

申请日：2021-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEORYONG PARK ,  SEUNGUK HAN ,  Jiyoung AHN ,  Kiseok LEE ,  YOONYOUNG CHOI ,  JISEOK HONG

IPC: H01L27/11551 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11578 ,  G11C7/18 ,  G11C8/14

Abstract: A semiconductor memory device includes a substrate with a cell array region, a first interface region, and a second interface region, the cell array region being provided with active regions, bit lines on the cell array region and the second interface region, dielectric patterns on top surfaces of the bit lines and extending along the top surfaces of the bit lines and further extending onto the first interface region, a device isolation pattern on the substrate, and including a first portion on the cell array region and a second portion on the first interface region, the first portion defining the active regions, the second portion being provided with first recesses, and each first recess being disposed between two adjacent dielectric patterns, and first sacrificial semiconductor patterns disposed on the first interface region and in the first recesses. The first sacrificial semiconductor patterns include polycrystalline silicon.

公开(公告)号：US20210125980A1

公开(公告)日：2021-04-29

申请号：US17132699

申请日：2020-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Dongoh KIM ,  Myeong-Dong LEE

IPC: H01L27/06 ,  H01L21/8238 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49

Abstract: Disclosed is a semiconductor device comprising a substrate including a first region and a second region, a first gate pattern on the substrate of the first region, and a second gate pattern on the substrate of the second region. The first gate pattern comprises a first high-k dielectric pattern, a first N-type metal-containing pattern, and a first P-type metal-containing pattern that are sequentially stacked. The second gate pattern comprises a second high-k dielectric pattern and a second P-type metal-containing pattern that are sequentially stacked.

公开(公告)号：US20190326278A1

公开(公告)日：2019-10-24

申请号：US16288590

申请日：2019-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Dongoh KIM ,  Myeong-Dong LEE

IPC: H01L27/06 ,  H01L21/8238 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49

Abstract: Disclosed is a semiconductor device comprising a substrate including a first region and a second region, a first gate pattern on the substrate of the first region, and a second gate pattern on the substrate of the second region. The first gate pattern comprises a first high-k dielectric pattern, a first N-type metal-containing pattern, and a first P-type metal-containing pattern that are sequentially stacked. The second gate pattern comprises a second high-k dielectric pattern and a second P-type metal-containing pattern that are sequentially stacked.

公开(公告)号：US20180158871A1

公开(公告)日：2018-06-07

申请号：US15653198

申请日：2017-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Augustin HONG ,  Keunnam KIM ,  Dongoh KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Hoin LEE ,  Sungho JANG ,  Kiwook JUNG ,  Yoosang HWANG

IPC: H01L27/24 ,  H01L27/22 ,  H01L27/108

CPC classification number: H01L27/10894 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10876 ,  H01L27/10897 ,  H01L27/228 ,  H01L27/2436

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.