公开(公告)号：US20240324186A1

公开(公告)日：2024-09-26

申请号：US18405026

申请日：2024-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KISEOK LEE ,  Chansic YOON

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34

Abstract: A semiconductor device includes active patterns on a substrate, gate structures in recesses of the active patterns and extending in the first direction, first contact plugs electrically connected to opposite edge portions of each of the active patterns, respectively, the first contact plugs being spaced apart from each other in each of the first and second directions and aligned in each of the first and second directions, first insulation spacers surrounding sidewalls of the first contact plugs, the first insulation spacers filling spaces between the first contact plugs in the second direction, a bit line structure filling an opening extending in the second direction between the first insulation spacers, the bit line structure contacting central portions of the active patterns, and a capacitor electrically connected to each of the first contact plugs.

公开(公告)号：US20230253318A1

公开(公告)日：2023-08-10

申请号：US18062811

申请日：2022-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok LEE ,  Chansic YOON ,  Keunnam KIM

IPC: H01L23/528 ,  H10B12/00

CPC classification number: H01L23/5283 ,  H01L27/10888 ,  H01L27/10891 ,  H01L27/10885 ,  H01L27/10814

Abstract: A semiconductor device includes a substrate including an active region, a word line structure, a bit line structure on the substrate, and a bit line contact pattern configured to electrically connect a first impurity region of the active region with the bit line structure. The device includes a storage node contact on a side wall of the bit line structure, and the storage node contact is electrically connected to a second impurity region of the active region. The device includes a spacer structure on a side wall of the bit line structure, the spacer structure on a side wall of the bit line contact pattern, the spacer structure including a lower spacer structure surrounding a side surface of the lower portion, and an upper spacer structure disposed on a side surface of the upper portion. The device includes a capacitor structure electrically connected to the storage node contact.

公开(公告)号：US20240315005A1

公开(公告)日：2024-09-19

申请号：US18388266

申请日：2023-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Sangjae PARK ,  Huijung KIM ,  Taejin PARK ,  Chansic YOON ,  Myeongdong LEE

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/482

Abstract: A semiconductor device includes an active pattern array including active patterns on a substrate; a first contact structure on a central portion of each active pattern; a bit line structure on the first contact structure; a second contact structure on an end of each active pattern; a third contact structure on the second contact structure; and a capacitor electrically connected to the third contact structure, wherein the active pattern array includes active pattern rows spaced apart from each other in a second direction parallel the substrate, the active pattern rows include active patterns spaced apart from each other in a first direction parallel to the substrate, the active patterns extend in a third direction having an acute angle with the first/second directions, the active patterns in the rows are aligned in the first direction, and the second contact structure has a rectangular shape in a plan view.

公开(公告)号：US20230113028A1

公开(公告)日：2023-04-13

申请号：US17750723

申请日：2022-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyebin CHOI ,  Chansic YOON ,  Gyuhyun KIL ,  Doosan BACK ,  Hyungki CHO ,  Junghoon HAN

IPC: H01L27/108 ,  H01L29/66

Abstract: A semiconductor device including a gate structure on a substrate, a first gate spacer, and a second gate spacer may be provided. A sidewall of the gate structure includes a concave lower sidewall portion and an upper sidewall portion that is vertical with respect to an upper surface of the substrate. The first gate spacer is formed on the upper sidewall portion of the sidewall of the gate structure. The second gate spacer is formed on the concave lower sidewall portion of the sidewall of the gate structure and an outer sidewall of the first gate spacer. The second gate spacer contacts a lower surface of the first gate spacer and includes nitride.

公开(公告)号：US20240284657A1

公开(公告)日：2024-08-22

申请号：US18529698

申请日：2023-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minho CHOI ,  Kiseok LEE ,  Chansic YOON ,  Chulkwon PARK ,  Jaybok CHOI

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/315 ,  H10B12/482

Abstract: A semiconductor device includes a substrate having a plurality of active regions and defining a plurality of first gate trenches and a plurality of second gate trenches crossing the plurality of active regions and extending in a first horizontal direction, a plurality of gate structures including a plurality of first gate structures within the plurality of first gate trenches and a plurality of second gate structures within the plurality of second gate trenches, a bit line structure crossing the plurality of gate structures and extending in a second horizontal direction that intersects the first horizontal direction, and a contact plug disposed on a side surface of the bit line structure. When viewed in plan view, an area of at least some of the plurality of first gate structures is different from an area of at least some of the plurality of second gate structures.

公开(公告)号：US20230320074A1

公开(公告)日：2023-10-05

申请号：US17948796

申请日：2022-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Jongmin KIM ,  Chansic YOON ,  Hyosub KIM ,  Sohyun PARK ,  Junhyeok AHN

IPC: H01L27/108 ,  H01L29/417

CPC classification number: H01L27/10814 ,  H01L29/41725

Abstract: Provided is a semiconductor device including a conductive contact plug on a substrate, the conductive contact plug including a lower portion and an upper portion on the lower portion, the lower portion having a first width, and the upper portion having a second width less than the first width, a bit line structure on the conductive contact plug, the bit line structure including a conductive structure and an insulation structure provided in a vertical direction perpendicular to an upper surface of the substrate, and a first lower spacer, a second lower spacer, and a third lower spacer sequentially provided on a sidewall of the lower portion of the conductive contact plug in a horizontal direction parallel to the upper surface of the substrate, wherein an uppermost surface of the third lower spacer is higher than an upper surface of the first lower spacer and an upper surface of the second lower spacer.

公开(公告)号：US20230178634A1

公开(公告)日：2023-06-08

申请号：US18072784

申请日：2022-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonil LEE ,  Gyuhyun KIL ,  Doosan BACK ,  Chansic YOON ,  Junghoon HAN

IPC: H01L29/66 ,  H10B12/00 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/6656 ,  H01L27/10897 ,  H01L27/10894 ,  H01L29/7833 ,  H01L29/6659 ,  H01L29/42364 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10823

Abstract: A semiconductor device includes a substrate, a gate dielectric layer on the substrate, the gate dielectric layer including a recess at a side surface thereof, a gate electrode structure on the gate dielectric layer, a gate capping layer on the gate electrode structure, and a spacer structure on the substrate and covering side surfaces of the gate dielectric layer, the gate electrode structure, and the gate capping layer, the spacer structure including a first spacer, a second spacer on the first spacer and covering the recess, and a third spacer on the second spacer, the second spacer and the third spacer including silicon nitride.

公开(公告)号：US20240274664A1

公开(公告)日：2024-08-15

申请号：US18409269

申请日：2024-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin JU ,  Chansic YOON ,  Gyuhyun KIL ,  Junghoon HAN ,  Weonhong KIM

IPC: H01L29/08 ,  H10B12/00

CPC classification number: H01L29/0847 ,  H10B12/50

Abstract: An integrated circuit device includes a gate stack on a substrate, a spacer on first and second sidewalls of the gate stack, a source/drain area in an upper portion of the substrate on first and second sides of the gate stack, a cover semiconductor layer on the source/drain area, an interlayer insulating film on the cover semiconductor layer and surrounding sidewalls of the gate stack, and a contact in a contact hole that penetrates the interlayer insulating film and the cover semiconductor layer, the contact having a bottom portion contacting the cover semiconductor layer and the source/drain area.

公开(公告)号：US20240147710A1

公开(公告)日：2024-05-02

申请号：US18457756

申请日：2023-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin KIM ,  Chansic YOON

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/09 ,  H10B12/315

Abstract: A semiconductor device may include a substrate including a cell region and a connection region, a cell word line extending across the plurality of active regions in a first horizontal direction on the cell region of the substrate, a cell bit line including a cell metallic conductive pattern extending on the cell region of the substrate in a second horizontal direction, and a connection bit line including a connection metallic conductive pattern extending in the second horizontal direction on the connection region of the substrate. A top surface of the connection bit line may be located at a vertical level that is equal to or lower than a top surface of the cell bit line, and a height of the connection metallic conductive pattern in a vertical direction may be equal to or greater than a height of the cell metallic conductive pattern in the vertical direction.

公开(公告)号：US20240130118A1

公开(公告)日：2024-04-18

申请号：US18138495

申请日：2023-04-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongmin KIM ,  Chansic YOON

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/09 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes: a substrate including a plurality of active regions in a memory cell region and at least one logic active region in a peripheral circuit region; a word line extending in a first horizontal direction on the plurality of active regions; a bit line structure extending in a second horizontal direction orthogonal to the first horizontal direction, on the plurality of active regions, and including a bit line, a cover insulating structure on a side surface of an end of the bit line, and an insulating capping structure on the bit line and the cover insulating structure; and a gate line on the at least one logic active region