知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

5 records (took 0.035 seconds)

    SEMICONDUCTOR DEVICE HAVING DEVICE ISOLATION LAYERS
    1.
    发明公开
    SEMICONDUCTOR DEVICE HAVING DEVICE ISOLATION LAYERS 审中-公开

    公开(公告)号：US20240290833A1

    公开(公告)日：2024-08-29

    申请号：US18537552

    申请日：2023-12-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minho CHOI ,  Kiseok LEE ,  Chansic YOON ,  Jaybok CHOI

    IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H10B12/00

    CPC classification number: H01L29/0649 ,  H01L29/4236 ,  H01L29/7855 ,  H10B12/482

    Abstract: A semiconductor device includes device isolation layers extending in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction, active regions between the device isolation layers and spaced apart from each other in the first horizontal direction, insulating structures between the active regions, and a gate structure extending in a third horizontal direction between the first horizontal direction and the second horizontal direction and intersecting the active regions, wherein two side surfaces of each active region adjacent to each other define an acute angle, and wherein at least a portion of at least one of the insulating structures is between a corresponding pair of the active regions and between a corresponding pair of the device isolation layers and overlaps the corresponding pair of the active regions in the first horizontal direction.

    SEMICONDUCTOR DEVICES HAVING GATE STRUCTURES
    2.
    发明公开
    SEMICONDUCTOR DEVICES HAVING GATE STRUCTURES 审中-公开

    公开(公告)号：US20240284657A1

    公开(公告)日：2024-08-22

    申请号：US18529698

    申请日：2023-12-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minho CHOI ,  Kiseok LEE ,  Chansic YOON ,  Chulkwon PARK ,  Jaybok CHOI

    IPC: H10B12/00

    CPC classification number: H10B12/34 ,  H10B12/315 ,  H10B12/482

    Abstract: A semiconductor device includes a substrate having a plurality of active regions and defining a plurality of first gate trenches and a plurality of second gate trenches crossing the plurality of active regions and extending in a first horizontal direction, a plurality of gate structures including a plurality of first gate structures within the plurality of first gate trenches and a plurality of second gate structures within the plurality of second gate trenches, a bit line structure crossing the plurality of gate structures and extending in a second horizontal direction that intersects the first horizontal direction, and a contact plug disposed on a side surface of the bit line structure. When viewed in plan view, an area of at least some of the plurality of first gate structures is different from an area of at least some of the plurality of second gate structures.

Patent Agency Ranking