公开(公告)号：US20240284657A1

公开(公告)日：2024-08-22

申请号：US18529698

申请日：2023-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minho CHOI ,  Kiseok LEE ,  Chansic YOON ,  Chulkwon PARK ,  Jaybok CHOI

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/315 ,  H10B12/482

Abstract: A semiconductor device includes a substrate having a plurality of active regions and defining a plurality of first gate trenches and a plurality of second gate trenches crossing the plurality of active regions and extending in a first horizontal direction, a plurality of gate structures including a plurality of first gate structures within the plurality of first gate trenches and a plurality of second gate structures within the plurality of second gate trenches, a bit line structure crossing the plurality of gate structures and extending in a second horizontal direction that intersects the first horizontal direction, and a contact plug disposed on a side surface of the bit line structure. When viewed in plan view, an area of at least some of the plurality of first gate structures is different from an area of at least some of the plurality of second gate structures.

公开(公告)号：US20240290833A1

公开(公告)日：2024-08-29

申请号：US18537552

申请日：2023-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minho CHOI ,  Kiseok LEE ,  Chansic YOON ,  Jaybok CHOI

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H10B12/00

CPC classification number: H01L29/0649 ,  H01L29/4236 ,  H01L29/7855 ,  H10B12/482

Abstract: A semiconductor device includes device isolation layers extending in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction, active regions between the device isolation layers and spaced apart from each other in the first horizontal direction, insulating structures between the active regions, and a gate structure extending in a third horizontal direction between the first horizontal direction and the second horizontal direction and intersecting the active regions, wherein two side surfaces of each active region adjacent to each other define an acute angle, and wherein at least a portion of at least one of the insulating structures is between a corresponding pair of the active regions and between a corresponding pair of the device isolation layers and overlaps the corresponding pair of the active regions in the first horizontal direction.

公开(公告)号：US20220271043A1

公开(公告)日：2022-08-25

申请号：US17744026

申请日：2022-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaybok CHOI ,  Yongseok AHN ,  Seunghyung LEE

IPC: H01L27/108 ,  H01L21/308 ,  H01L21/762 ,  H01L21/306

Abstract: A method of manufacturing an integrated circuit device includes: over a substrate, forming first hard mask patterns extending in a first direction parallel to a top surface of the substrate and arranged at a first pitch in a second direction; forming a plurality of first trenches in the substrate using the first hard mask patterns as etching masks; forming a plurality of first gate electrodes on inner walls of the plurality of first trenches; over the substrate, forming second hard mask patterns extending in the first direction and arranged at a second pitch in the second direction; forming a plurality of second trenches in the substrate using the second hard mask patterns as etching masks, each of the plurality of second trenches being disposed between two adjacent first trenches; and forming a plurality of second gate electrodes on inner walls of the plurality of second trenches.

公开(公告)号：US20210104529A1

公开(公告)日：2021-04-08

申请号：US16902506

申请日：2020-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaybok CHOI ,  Yongseok AHN ,  Seunghyung LEE

IPC: H01L27/108 ,  H01L21/308 ,  H01L21/306 ,  H01L21/762

Abstract: A method of manufacturing an integrated circuit device includes: over a substrate, forming first hard mask patterns extending in a first direction parallel to a top surface of the substrate and arranged at a first pitch in a second direction; forming a plurality of first trenches in the substrate using the first hard mask patterns as etching masks; forming a plurality of first gate electrodes on inner walls of the plurality of first trenches; over the substrate, forming second hard mask patterns extending in the first direction and arranged at a second pitch in the second direction; forming a plurality of second trenches in the substrate using the second hard mask patterns as etching masks, each of the plurality of second trenches being disposed between two adjacent first trenches; and forming a plurality of second gate electrodes on inner walls of the plurality of second trenches.