公开(公告)号：US20220335709A1

公开(公告)日：2022-10-20

申请号：US17695142

申请日：2022-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geunhee YANG ,  Donghoon KIM ,  Maiyuran WIJAY ,  Oleg Sergeyevich KHORUZHIY ,  Rama Mythili VADALI ,  Song NI ,  Dusic YOO ,  Jaewon YU ,  Seunghyung LEE ,  Venkata Rama Krishna MEKA

IPC: G06V10/764 ,  G06T5/00 ,  G06V10/26 ,  G06T3/40 ,  G06V20/00 ,  G06V10/774 ,  G06N3/08

Abstract: Provided are an image processing circuit, a system-on-chip including the same, and a method of improving quality of a first image. The image processing circuit includes a tuning circuit configured to receive a segmentation map including pixel-by-pixel class inference information of the first image and a confidence map including confidence of the class inference information, determine classes of respective pixels of the first image, correction effects for each pixel of the image, and correction values indicating intensity of the correction effects based on the segmentation map and the confidence map, and generate a correction map based on the classes and the correction values of the respective pixels; and at least one correcting circuit configured to generate an enhanced image by applying correction effects according to the correction values to the respective pixels of the first image based on the correction map.

公开(公告)号：US20220271043A1

公开(公告)日：2022-08-25

申请号：US17744026

申请日：2022-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaybok CHOI ,  Yongseok AHN ,  Seunghyung LEE

IPC: H01L27/108 ,  H01L21/308 ,  H01L21/762 ,  H01L21/306

Abstract: A method of manufacturing an integrated circuit device includes: over a substrate, forming first hard mask patterns extending in a first direction parallel to a top surface of the substrate and arranged at a first pitch in a second direction; forming a plurality of first trenches in the substrate using the first hard mask patterns as etching masks; forming a plurality of first gate electrodes on inner walls of the plurality of first trenches; over the substrate, forming second hard mask patterns extending in the first direction and arranged at a second pitch in the second direction; forming a plurality of second trenches in the substrate using the second hard mask patterns as etching masks, each of the plurality of second trenches being disposed between two adjacent first trenches; and forming a plurality of second gate electrodes on inner walls of the plurality of second trenches.

公开(公告)号：US20210104529A1

公开(公告)日：2021-04-08

申请号：US16902506

申请日：2020-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaybok CHOI ,  Yongseok AHN ,  Seunghyung LEE

IPC: H01L27/108 ,  H01L21/308 ,  H01L21/306 ,  H01L21/762

Abstract: A method of manufacturing an integrated circuit device includes: over a substrate, forming first hard mask patterns extending in a first direction parallel to a top surface of the substrate and arranged at a first pitch in a second direction; forming a plurality of first trenches in the substrate using the first hard mask patterns as etching masks; forming a plurality of first gate electrodes on inner walls of the plurality of first trenches; over the substrate, forming second hard mask patterns extending in the first direction and arranged at a second pitch in the second direction; forming a plurality of second trenches in the substrate using the second hard mask patterns as etching masks, each of the plurality of second trenches being disposed between two adjacent first trenches; and forming a plurality of second gate electrodes on inner walls of the plurality of second trenches.