公开(公告)号：US20240349490A1

公开(公告)日：2024-10-17

申请号：US18501980

申请日：2023-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Huije RYU ,  Hyungki CHO

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/488

Abstract: A semiconductor memory device includes a bit line that extends in a first direction, semiconductor patterns disposed on the bit line and spaced apart from each other in the first direction and each including a first vertical part, a second vertical part, and a horizontal part, first and second word lines disposed on the horizontal part and respectively adjacent to the first and second vertical parts, and a semiconductor dielectric pattern disposed on the bit line and between the semiconductor patterns. The semiconductor dielectric pattern includes a lower capping pattern, sidewall dielectric patterns spaced apart from each other in the first direction on the lower capping pattern, an air gap between the sidewall dielectric patterns, and an upper capping pattern disposed on the sidewall dielectric patterns. Top surfaces of the sidewall dielectric patterns are at the same height as top surfaces of the first and second vertical parts.

公开(公告)号：US20250142908A1

公开(公告)日：2025-05-01

申请号：US18738107

申请日：2024-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungki CHO ,  Seongjae BYEON

IPC: H01L29/10 ,  H01L23/31 ,  H01L23/522 ,  H01L27/06 ,  H01L29/24

Abstract: A semiconductor device includes: a mold insulating pattern positioned on a substrate; an upper conductive line extending in a first horizontal direction on the substrate; a channel structure including a vertical channel portion that faces a side surface of the upper conductive line, and is in contact with a first side wall of the mold insulating pattern, wherein the vertical channel portion extends in a vertical direction; a first gate dielectric layer at least partially surround a surface of the channel structure; and a second gate dielectric layer positioned between the upper conductive line and the first gate dielectric layer on the channel structure, wherein the mold insulating pattern includes a body and protrusion, wherein the body extends in the first horizontal direction, and the protrusion protrude in a second horizontal direction that intersects with the first horizontal direction.

公开(公告)号：US20230113028A1

公开(公告)日：2023-04-13

申请号：US17750723

申请日：2022-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyebin CHOI ,  Chansic YOON ,  Gyuhyun KIL ,  Doosan BACK ,  Hyungki CHO ,  Junghoon HAN

IPC: H01L27/108 ,  H01L29/66

Abstract: A semiconductor device including a gate structure on a substrate, a first gate spacer, and a second gate spacer may be provided. A sidewall of the gate structure includes a concave lower sidewall portion and an upper sidewall portion that is vertical with respect to an upper surface of the substrate. The first gate spacer is formed on the upper sidewall portion of the sidewall of the gate structure. The second gate spacer is formed on the concave lower sidewall portion of the sidewall of the gate structure and an outer sidewall of the first gate spacer. The second gate spacer contacts a lower surface of the first gate spacer and includes nitride.