公开(公告)号：US20240274664A1

公开(公告)日：2024-08-15

申请号：US18409269

申请日：2024-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin JU ,  Chansic YOON ,  Gyuhyun KIL ,  Junghoon HAN ,  Weonhong KIM

IPC: H01L29/08 ,  H10B12/00

CPC classification number: H01L29/0847 ,  H10B12/50

Abstract: An integrated circuit device includes a gate stack on a substrate, a spacer on first and second sidewalls of the gate stack, a source/drain area in an upper portion of the substrate on first and second sides of the gate stack, a cover semiconductor layer on the source/drain area, an interlayer insulating film on the cover semiconductor layer and surrounding sidewalls of the gate stack, and a contact in a contact hole that penetrates the interlayer insulating film and the cover semiconductor layer, the contact having a bottom portion contacting the cover semiconductor layer and the source/drain area.

公开(公告)号：US20230247826A1

公开(公告)日：2023-08-03

申请号：US18099302

申请日：2023-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyebin CHOI ,  Chansic YOON ,  Gyuhyun KIL

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/34 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor device includes an active region, a gate dielectric layer disposed on the active region, a gate electrode disposed on the gate dielectric layer, a protective layer in contact with a portion of a side surface of the gate electrode, and a spacer structure covering the side surface of the gate electrode and the protective layer. The gate electrode includes a lower conductive pattern disposed on the gate dielectric layer, an intermediate conductive pattern disposed on the lower conductive pattern, and an upper conductive pattern disposed on the intermediate conductive pattern. The protective layer includes a first protective portion in contact with at least a portion of a side surface of the intermediate conductive pattern and a second protective portion in contact with a side surface of the upper conductive pattern, and the second protective portion includes a material different from a material of the first protective portion.

公开(公告)号：US20230354589A1

公开(公告)日：2023-11-02

申请号：US18220323

申请日：2023-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongoh KIM ,  Gyuhyun KIL ,  Junghoon HAN ,  Doosan BACK

IPC: H01L27/108 ,  H01L27/092

CPC classification number: H10B12/50 ,  H01L27/092 ,  H10B12/315

Abstract: A semiconductor device includes first and second trenches in respective first and second regions in a substrate, a first isolation structure having a first inner wall oxide pattern, a first liner, and a first filling insulation pattern sequentially stacked I the first trench, a second isolation structure having a second inner wall oxide pattern, a second liner, and a second filling insulation pattern sequentially stacked I the second trench, a first gate structure having a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked on the first region, and a second gate structure having a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked on the second region, wherein the first and second liners protrude above upper surfaces of the first and second inner wall oxide patterns and the first and second filling insulation patterns, respectively.

公开(公告)号：US20230113028A1

公开(公告)日：2023-04-13

申请号：US17750723

申请日：2022-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyebin CHOI ,  Chansic YOON ,  Gyuhyun KIL ,  Doosan BACK ,  Hyungki CHO ,  Junghoon HAN

IPC: H01L27/108 ,  H01L29/66

Abstract: A semiconductor device including a gate structure on a substrate, a first gate spacer, and a second gate spacer may be provided. A sidewall of the gate structure includes a concave lower sidewall portion and an upper sidewall portion that is vertical with respect to an upper surface of the substrate. The first gate spacer is formed on the upper sidewall portion of the sidewall of the gate structure. The second gate spacer is formed on the concave lower sidewall portion of the sidewall of the gate structure and an outer sidewall of the first gate spacer. The second gate spacer contacts a lower surface of the first gate spacer and includes nitride.

公开(公告)号：US20230354590A1

公开(公告)日：2023-11-02

申请号：US18220327

申请日：2023-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongoh KIM ,  Gyuhyun KIL ,  Junghoon HAN ,  Doosan BACK

IPC: H10B12/00 ,  H01L27/092

CPC classification number: H10B12/50 ,  H01L27/092 ,  H10B12/315

Abstract: A semiconductor device includes first and second trenches in respective first and second regions in a substrate, a first isolation structure having a first inner wall oxide pattern, a first liner, and a first filling insulation pattern sequentially stacked I the first trench, a second isolation structure having a second inner wall oxide pattern, a second liner, and a second filling insulation pattern sequentially stacked I the second trench, a first gate structure having a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked on the first region, and a second gate structure having a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked on the second region, wherein the first and second liners protrude above upper surfaces of the first and second inner wall oxide patterns and the first and second filling insulation patterns, respectively.

公开(公告)号：US20230178634A1

公开(公告)日：2023-06-08

申请号：US18072784

申请日：2022-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonil LEE ,  Gyuhyun KIL ,  Doosan BACK ,  Chansic YOON ,  Junghoon HAN

IPC: H01L29/66 ,  H10B12/00 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/6656 ,  H01L27/10897 ,  H01L27/10894 ,  H01L29/7833 ,  H01L29/6659 ,  H01L29/42364 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10823

Abstract: A semiconductor device includes a substrate, a gate dielectric layer on the substrate, the gate dielectric layer including a recess at a side surface thereof, a gate electrode structure on the gate dielectric layer, a gate capping layer on the gate electrode structure, and a spacer structure on the substrate and covering side surfaces of the gate dielectric layer, the gate electrode structure, and the gate capping layer, the spacer structure including a first spacer, a second spacer on the first spacer and covering the recess, and a third spacer on the second spacer, the second spacer and the third spacer including silicon nitride.

公开(公告)号：US20220189969A1

公开(公告)日：2022-06-16

申请号：US17386008

申请日：2021-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongoh KIM ,  Gyuhyun KIL ,  Junghoon HAN ,  Doosan BACK

IPC: H01L27/108 ,  H01L27/092

Abstract: A semiconductor device includes first and second trenches in respective first and second regions in a substrate, a first isolation structure having a first inner wall oxide pattern, a first liner, and a first filling insulation pattern sequentially stacked I the first trench, a second isolation structure having a second inner wall oxide pattern, a second liner, and a second filling insulation pattern sequentially stacked I the second trench, a first gate structure having a first high-k dielectric pattern, a first P-type metal pattern, and a first N-type metal pattern sequentially stacked on the first region, and a second gate structure having a second high-k dielectric pattern and a second N-type metal pattern sequentially stacked on the second region, wherein the first and second liners protrude above upper surfaces of the first and second inner wall oxide patterns and the first and second filling insulation patterns, respectively.

公开(公告)号：US20220189967A1

公开(公告)日：2022-06-16

申请号：US17371558

申请日：2021-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongoh KIM ,  Gyuhyun KIL ,  Junghoon HAN ,  Doosan BACK

IPC: H01L27/108

Abstract: A semiconductor memory device may have a substrate including an active region in a memory cell region and a logic active region in a peripheral region, an element isolation structure between the active region and the logic active region, an insulating layer pattern covering the active region, and a support insulating layer. The insulating layer pattern may include an extension portion that extends along the element isolation structure, may be spaced apart from the element isolation structure, and may overhang over the element isolation structure. The support insulating layer may fill a recess space defined between the extension portion and the element isolation structure.