公开(公告)号：US20230247826A1

公开(公告)日：2023-08-03

申请号：US18099302

申请日：2023-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyebin CHOI ,  Chansic YOON ,  Gyuhyun KIL

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/34 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor device includes an active region, a gate dielectric layer disposed on the active region, a gate electrode disposed on the gate dielectric layer, a protective layer in contact with a portion of a side surface of the gate electrode, and a spacer structure covering the side surface of the gate electrode and the protective layer. The gate electrode includes a lower conductive pattern disposed on the gate dielectric layer, an intermediate conductive pattern disposed on the lower conductive pattern, and an upper conductive pattern disposed on the intermediate conductive pattern. The protective layer includes a first protective portion in contact with at least a portion of a side surface of the intermediate conductive pattern and a second protective portion in contact with a side surface of the upper conductive pattern, and the second protective portion includes a material different from a material of the first protective portion.

公开(公告)号：US20230113028A1

公开(公告)日：2023-04-13

申请号：US17750723

申请日：2022-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyebin CHOI ,  Chansic YOON ,  Gyuhyun KIL ,  Doosan BACK ,  Hyungki CHO ,  Junghoon HAN

IPC: H01L27/108 ,  H01L29/66

Abstract: A semiconductor device including a gate structure on a substrate, a first gate spacer, and a second gate spacer may be provided. A sidewall of the gate structure includes a concave lower sidewall portion and an upper sidewall portion that is vertical with respect to an upper surface of the substrate. The first gate spacer is formed on the upper sidewall portion of the sidewall of the gate structure. The second gate spacer is formed on the concave lower sidewall portion of the sidewall of the gate structure and an outer sidewall of the first gate spacer. The second gate spacer contacts a lower surface of the first gate spacer and includes nitride.

公开(公告)号：US20240172417A1

公开(公告)日：2024-05-23

申请号：US18420138

申请日：2024-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyeon BAE ,  Wonchul LEE ,  Jaehyun KIM ,  Jaehyuk JANG ,  Hyebin CHOI

IPC: H10B12/00 ,  H01L23/528

CPC classification number: H10B12/315 ,  H01L23/528

Abstract: A semiconductor device includes a gate structure and a contact plug. The gate structure extends in a first direction parallel to the substrate, and includes a first conductive pattern, a second conductive pattern and a gate mask sequentially stacked. The contact plug contacts an end portion in the first direction of the gate structure, and includes a first extension portion extending in a vertical direction and contacting sidewalls of the gate mask and the second conductive pattern, a second extension portion under and contacting the first extension portion and a sidewall of the first conductive pattern, and a protrusion portion under and contacting the second extension portion. A bottom of the protrusion portion does not contact the first conductive pattern. A first slope of a sidewall of the first extension portion is greater than a second slope of a sidewall of the second extension portion.

公开(公告)号：US20220271041A1

公开(公告)日：2022-08-25

申请号：US17484679

申请日：2021-09-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sohyeon BAE ,  Wonchul LEE ,  Jaehyun KIM ,  Jaehyuk JANG ,  Hyebin CHOI

IPC: H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes a gate structure and a contact plug. The gate structure extends in a first direction parallel to the substrate, and includes a first conductive pattern, a second conductive pattern and a gate mask sequentially stacked. The contact plug contacts an end portion in the first direction of the gate structure, and includes a first extension portion extending in a vertical direction and contacting sidewalls of the gate mask and the second conductive pattern, a second extension portion under and contacting the first extension portion and a sidewall of the first conductive pattern, and a protrusion portion under and contacting the second extension portion. A bottom of the protrusion portion does not contact the first conductive pattern. A first slope of a sidewall of the first extension portion is greater than a second slope of a sidewall of the second extension portion.