公开(公告)号：US09997208B1

公开(公告)日：2018-06-12

申请号：US15473124

申请日：2017-03-29

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Po-Hung Chen ,  Fahad Ahmed ,  Changho Jung ,  Sei Seung Yoon ,  David Li

IPC: G11C8/08 ,  G11C5/14 ,  H03K19/0185 ,  G11C8/10 ,  G11C7/12

CPC classification number: G11C5/147 ,  G11C7/12 ,  G11C8/10 ,  H03K3/356069 ,  H03K19/018528

Abstract: A circuit including an output node and a cross-coupled pair of semiconductor devices configured to provide, at the output node, an output signal in a second voltage domain based on an input signal in a first voltage domain is described herein. The circuit further includes a pull-up assist circuit coupled to the output node; and a look-ahead circuit coupled to the pull-up assist circuit, wherein the look-ahead circuit is configured to cause the pull-up assist circuit to assist in increasing a voltage level at the output node when there is a decrease in a voltage level of an inverted output signal in the second voltage domain from a high voltage level of the second voltage domain to a low voltage level of the second voltage domain.

公开(公告)号：US09978442B2

公开(公告)日：2018-05-22

申请号：US15258964

申请日：2016-09-07

Applicant: QUALCOMM Incorporated

Inventor： Bin Liang ,  Tony Chung Yiu Kwok ,  Rui Li ,  Sei Seung Yoon

IPC: G11C11/4076 ,  G11C7/14 ,  G11C11/418 ,  G11C11/419 ,  G11C7/10 ,  G11C13/00

CPC classification number: G11C11/418 ,  G11C7/1072 ,  G11C7/227 ,  G11C8/18 ,  G11C11/419 ,  G11C13/0061

Abstract: A memory is disclosed. The memory includes a memory array having a plurality of memory cells. The memory also includes an address decoder configured to assert a wordline to enable the memory cells. Additionally, the memory includes a tracking circuit configured to vary a duration of asserting the wordline as a function of which one of the memory cells is accessed. A method is also disclosed. The method includes asserting a wordline to enable the memory cells and varying a duration of asserting the wordline as a function of which one of a plurality of memory cells is accessed.

公开(公告)号：US09959912B2

公开(公告)日：2018-05-01

申请号：US15013897

申请日：2016-02-02

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Fahad Ahmed ,  Sei Seung Yoon ,  Keejong Kim

IPC: G11C7/02 ,  G11C7/00 ,  G11C7/08 ,  G11C7/14 ,  G11C11/418 ,  G11C11/419 ,  G11C29/02 ,  G11C29/14 ,  G11C29/50 ,  G11C5/06 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C7/02 ,  G11C5/06 ,  G11C7/00 ,  G11C7/062 ,  G11C7/08 ,  G11C7/10 ,  G11C7/14 ,  G11C11/418 ,  G11C11/419 ,  G11C29/02 ,  G11C29/026 ,  G11C29/14 ,  G11C29/50012

Abstract: A memory includes a memory cell, one bitline coupled to the memory cell, a sense amplifier coupled to the one bitline, a timing circuit configured to enable the sense amplifier during a read operation, a control circuit configured to enable the sense amplifier independent of the timing circuit, and a pull-up circuit configured to pull up the one bitline while the sense amplifier is enabled by the control circuit. The method includes enabling a sense amplifier in a read operation by a timing circuit. The sense amplifier is coupled to at least one bitline, and the at least one bitline is coupled to a memory cell. The method further includes enabling the sense amplifier independent of the timing circuit in a second operation and pulling up the at least one bitline by a pull-up circuit while the sense amplifier is enabled in the second operation.

公开(公告)号：US09748003B2

公开(公告)日：2017-08-29

申请号：US14485379

申请日：2014-09-12

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Sei Seung Yoon ,  Robert Henry Hoem

IPC: G11C8/12 ,  G11C29/00 ,  G11C11/418 ,  G11C17/16 ,  G11C17/18 ,  G11C8/10

CPC classification number: G11C29/781 ,  G11C8/10 ,  G11C8/12 ,  G11C11/418 ,  G11C17/16 ,  G11C17/18 ,  G11C29/76 ,  G11C29/802 ,  G11C29/806

Abstract: A system may be provided that provides redundancy for a plurality of embedded memories such as SRAMs. The system may include one or more decoders, each capable of decoding a selection address to identify a defective one of the embedded memories.

公开(公告)号：US09627041B1

公开(公告)日：2017-04-18

申请号：US15010385

申请日：2016-01-29

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Fahad Ahmed ,  Sei Seung Yoon ,  Keejong Kim

IPC: G11C11/00 ,  G11C11/419 ,  G11C5/14 ,  G11C11/4074

CPC classification number: G11C11/419 ,  G11C5/147 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/417 ,  G11C11/418 ,  G11C29/12005 ,  G11C2029/1202

Abstract: A memory and a method to operate the memory are provided. The memory includes a plurality of memory cells and a wordline driver configured to output a wordline. The memory cells are coupled to the wordline. A control circuit is configured to supply an operating voltage to the memory cells and to the wordline driver. A voltage-adjustment circuit is configured to adjust the operating voltage supplied to the memory cells during the control circuit supplying the operating voltage to the memory cells and to the wordline driver. The method includes supplying an operating voltage to at least one memory cells and to a wordline coupled to the at least one memory cells and adjusting the operating voltage supplied to the at least one memory cells during the supplying the operating voltage to the at least one memory cells and to the wordline.

公开(公告)号：US20160276005A1

公开(公告)日：2016-09-22

申请号：US15070963

申请日：2016-03-15

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Po-Hung Chen ,  David Li ,  Sei Seung Yoon

IPC: G11C8/08 ,  G11C8/10 ,  G11C5/14

CPC classification number: G11C8/08 ,  G11C5/14 ,  G11C8/06 ,  G11C8/10

Abstract: A memory is provided that includes a row decoder that decodes an address into a plurality of decoded signals for selecting a word line to be asserted from a plurality of word lines. Each word line is driven through a decoder level-shifter that processes the decoded signals. Each decoder level-shifter corresponds to a unique combination of the decoded signals. The row decoder is in a logic power domain such that the decoded signals are asserted to a logic power supply voltage. When a decoder level-shifter's unique combination of decoded signals are asserted by the row decoder, the decoder level-shifter drives the corresponding word line with a memory power supply voltage for a memory power domain.

Abstract translation: 提供了一种存储器，其包括行解码器，其将地址解码为用于从多个字线选择要断言的字线的多个解码信号。 每个字线通过处理解码信号的解码器电平转换器驱动。 每个解码器电平转换器对应于解码信号的唯一组合。 行解码器处于逻辑功率域，使得解码信号被断言为逻辑电源电压。 当解码器电平移位器的解码信号的唯一组合由行解码器确定时，解码器电平转换器用存储器电源域的存储器电源电压驱动相应的字线。

公开(公告)号：US20160078969A1

公开(公告)日：2016-03-17

申请号：US14485379

申请日：2014-09-12

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Sei Seung Yoon ,  Robert Henry Hoem

IPC: G11C29/00 ,  G11C17/18 ,  G11C11/418 ,  G11C17/16

CPC classification number: G11C29/781 ,  G11C8/10 ,  G11C8/12 ,  G11C11/418 ,  G11C17/16 ,  G11C17/18 ,  G11C29/76 ,  G11C29/802 ,  G11C29/806

Abstract: A system may be provided that provides redundancy for a plurality of embedded memories such as SRAMs. The system may include one or more decoders, each capable of decoding a selection address to identify a defective one of the embedded memories.

Abstract translation: 可以提供为诸如SRAM之类的多个嵌入存储器提供冗余的系统。 系统可以包括一个或多个解码器，每个解码器能够解码选择地址以识别嵌入存储器中的有缺陷的一个。

公开(公告)号：US09082498B2

公开(公告)日：2015-07-14

申请号：US13962702

申请日：2013-08-08

Applicant: QUALCOMM Incorporated

Inventor： Gregory Ameriada Uvieghara ,  Sei Seung Yoon

IPC: G11C7/00 ,  G11C17/18 ,  G11C17/16 ,  H03K3/356

CPC classification number: G11C17/18 ,  G11C16/12 ,  G11C17/16 ,  H03K3/356113

Abstract: A thin gate-oxide dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit is configured to bias the switched n-well to prevent voltage damage to the dual-mode PMOS transistor without the use of native transistors.

Abstract translation: 公开了一种薄栅氧化物双模PMOS晶体管，其具有第一工作模式，其中双模PMOS晶体管的开关n阱被偏置到高电压。 双模式PMOS晶体管具有第二工作模式，其中开关n阱被偏置成低于高电压的低电压。 双模式PMOS晶体管的尺寸和栅极氧化物厚度各自具有不能适应与高电压的永久连接的幅度。 n阱电压开关电路被配置为偏置开关n阱以防止对双模PMOS晶体管的电压损坏，而不使用天然晶体管。

公开(公告)号：US09071239B2

公开(公告)日：2015-06-30

申请号：US13799686

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Sei Seung Yoon ,  Esin Terzioglu ,  Hari Ananthanarayanan ,  Venugopal Boynapalli

IPC: H03K17/00 ,  G11C7/10 ,  G11C7/02

CPC classification number: H03K17/002 ,  G11C7/02 ,  G11C7/10 ,  G11C7/1006

Abstract: A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices.

Abstract translation: 本发明提供一种半导体装置，用于在半导体装置中的第一装置和第二装置之间传输数据时降低功率。 向半导体装置添加附加电路以创建通信系统，该通信系统减少用于所有通信的第一设备和第二设备之间的数据总线的每个信号线的状态变化的数量。 附加电路包括解码器，其耦合以接收和转换来自第一设备的值，用于通过数据总线传输到向第二设备提供值的恢复（即重新编码）版本的编码器。 一个或多个多路复用器也可以包括在附加电路中以支持任何数量的设备。

公开(公告)号：US08934278B2

公开(公告)日：2015-01-13

申请号：US13730487

申请日：2012-12-28

Applicant: QUALCOMM Incorporated

Inventor： Rakesh Vattikonda ,  Nishith Desai ,  ChangHo Jung ,  Sei Seung Yoon ,  Esin Terzioglu

IPC: G11C15/04 ,  G11C15/00

CPC classification number: G11C15/00 ,  G11C15/04

Abstract: A method within a hybrid ternary content addressable memory (TCAM) includes comparing a first portion of a search word to a first portion of a stored word in a first TCAM stage. The method further includes interfacing an output of the first TCAM stage to an input of the second TCAM stage. The method also includes comparing a second portion of the search word to a second portion of the stored word in a second TCAM stage when the first portion of the search word matches the first portion of the stored word. The first TCAM stage is different from the second TCAM stage.

Abstract translation: 混合三元内容可寻址存储器（TCAM）内的方法包括将搜索词的第一部分与第一TCAM级中的存储字的第一部分进行比较。 该方法还包括将第一TCAM级的输出与第二TCAM级的输入进行接口。 该方法还包括当搜索词的第一部分与存储的单词的第一部分匹配时，在第二TCAM阶段中将搜索词的第二部分与所存储的单词的第二部分进行比较。 第一个TCAM阶段与第二个TCAM阶段不同。