-
公开(公告)号：US20190189228A1
公开(公告)日：2019-06-20
申请号：US15890326
申请日：2018-02-06
发明人： Wei Lin , Yu-Hsiang Lin , Yu-Cheng Hsu
摘要： A bit tagging method, a memory control circuit unit and a memory storage device are provided. The method includes: reading first memory cells according to a first reading voltage to generate a first codeword and determining whether the first codeword is a valid codeword, and the first codeword includes X bits; if not, reading the first memory cells according to a second reading voltage to generate a second codeword and determining whether the second codeword is the valid codeword, and the second codeword includes X bits; and if the second codeword is not the valid codeword and a Yth bit in the X bits of the first codeword is different from a Yth bit in the X bits of the second codeword, recording the Yth bit in the X bits as an unreliable bit, and Y is a positive integer less than or equal to X.
-
公开(公告)号：US10310739B2
公开(公告)日：2019-06-04
申请号：US15690286
申请日：2017-08-30
发明人： Chien-Wen Chen , Che-Yueh Kuo
摘要： A memory management method is provided according to an exemplary embodiment of the disclosure. The method includes: obtaining a valid data parameter based on a valid data amount of valid data stored in a plurality of physical erasing units, and obtaining a first threshold value based on the valid data parameter. The method also includes: obtaining a first determination parameter based on a number of a plurality of first physical erasing units, and the first physical erasing units are physical erasing units being programmed for storing data by using a single-page programming mode. The method further includes: performing a garbage collection operation if the first determination parameter is greater than the first threshold value.
-
公开(公告)号：US10297297B2
公开(公告)日：2019-05-21
申请号：US14578471
申请日：2014-12-21
发明人： Jen-Chu Wu , Wei-Yung Chen
摘要： A sampling circuit module, a memory control circuit unit, and a data sampling method, where the sampling circuit module includes a delay lock loop (DLL) and a sampling circuit. The DLL includes a clock control circuit, a clock delay circuit and a voltage control circuit. The clock control circuit performs a delay lock for a reference clock signal, so as to output a selecting signal. The clock delay circuit delays the reference clock signal according to the selecting signal, so as to output a delay clock signal. The voltage control circuit adjusts a driving voltage outputted to the clock control circuit and the clock delay circuit according to the selecting signal. The sampling circuit samples a data signal according to the delay clock signal. Accordingly, a delay ability of the DLL may be improved by adjusting the driving voltage.
-
公开(公告)号：US10235094B2
公开(公告)日：2019-03-19
申请号：US15060622
申请日：2016-03-04
发明人： Bo-Cheng Ko
摘要： A data writing method, a memory control circuit unit, and a memory storage apparatus are provided. The method includes recording a flush command counting (FCC) value, and updating the FCC value whenever receiving a flush command from a host system. The method further includes getting a first physical erasing unit as an active physical unit and determining whether the FCC value is greater than a FCC value threshold. The method further includes setting a writing mode of the active physical unit as a first writing mode if the FCC value is greater than the FCC value threshold, and setting the writing mode of the active physical unit as a second writing mode if the FCC value is not greater than the FCC value threshold.
-
公开(公告)号：US20190065097A1
公开(公告)日：2019-02-28
申请号：US15798370
申请日：2017-10-30
发明人： Shao-Hsien Liu , Chien-Han Kuo
IPC分类号： G06F3/06
摘要： A data storage method is provided according to an exemplary embodiment of the disclosure. The method is configured for a rewritable non-volatile memory module. The method includes: performing a data merge operation; adjusting a data receiving amount per unit time for receiving to-be-written data from a host system according to a data storage state of the rewritable non-volatile memory module; storing the received to-be-written data into a buffer memory during the data merge operation being performed; and storing the data stored in the buffer memory into the rewritable non-volatile memory module.
-
公开(公告)号：US10203886B2
公开(公告)日：2019-02-12
申请号：US15080557
申请日：2016-03-24
发明人： Jia-Yan Huang
摘要： A data writing method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: determining whether receiving a predetermined command from a host system. The method also includes: if receiving the predetermined command from the host system, writing at least one buffer data from a buffer memory into a first physical erasing unit, selecting at least one second physical erasing unit from the physical erasing units, and writing at least one valid data of the at least one second physical erasing unit into the first physical erasing unit in response to the predetermined command.
-
公开(公告)号：US20190034329A1
公开(公告)日：2019-01-31
申请号：US15706765
申请日：2017-09-18
发明人： Chih-Kang Yeh
CPC分类号： G06F12/0246 , G06F3/0619 , G06F3/0631 , G06F3/0656 , G06F3/0679
摘要： An exemplary embodiment of the disclosure provides a data storage method for a rewritable non-volatile memory module. The method includes: receiving first data; mapping a logical unit of the first data to a first physical unit of a first management unit and not storing the first data to the rewritable non-volatile memory module if a data content of the first data is identical to a data content of second data, and the second data is stored in the first physical unit; and storing logical-to-physical bit map information to a second physical unit in the first management unit, and the logical-to-physical bit map information corresponds to at least one logical-to-physical mapping table and is configured for identifying valid data in the first management unit.
-
公开(公告)号：US10193569B2
公开(公告)日：2019-01-29
申请号：US14477867
申请日：2014-09-05
发明人： Chien-Fu Tseng , Tsai-Cheng Lin , Yen-Chiao Lai
摘要： A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: executing at least one first iteration decoding procedure of an LDPC on a first codeword according to a first clock signal by a correcting circuit; generating a control parameter according to a first iteration count of the first iteration decoding procedure; outputting a second clock signal to the correcting circuit according to the control parameter; and executing at least one second iteration decoding procedure of the LDPC on a second codeword according to the second clock signal by the correcting circuit.
-
公开(公告)号：US10193537B2
公开(公告)日：2019-01-29
申请号：US15487417
申请日：2017-04-13
发明人： Bing-Wei Yi
IPC分类号： H03K3/012 , H03K3/84 , H03K5/159 , H03K5/19 , G11C7/24 , G06F7/58 , G11C7/22 , H03K19/21 , G11C27/02
摘要： An exemplary embodiment of the disclosure provides a random data generation circuit which includes a phase difference detection circuit and a random data output circuit. The phase difference detection circuit detects a phase difference between a first clock signal and a second clock signal and outputs phase difference information. The random data output circuit is coupled to the phase difference detection circuit and outputs random data according to the phase difference information. Thereby, ideal and unpredictable random data is generated.
-
公开(公告)号：US20190012080A1
公开(公告)日：2019-01-10
申请号：US15690286
申请日：2017-08-30
发明人： Chien-Wen Chen , Che-Yueh Kuo
摘要： A memory management method is provided according to an exemplary embodiment of the disclosure. The method includes: obtaining a valid data parameter based on a valid data amount of valid data stored in a plurality of physical erasing units, and obtaining a first threshold value based on the valid data parameter. The method also includes: obtaining a first determination parameter based on a number of a plurality of first physical erasing units, and the first physical erasing units are physical erasing units being programmed for storing data by using a single-page programming mode. The method further includes: performing a garbage collection operation if the first determination parameter is greater than the first threshold value.
-
-
-
-
-
-
-
-
-
搜索结果
1220 条记录 (耗时 0.036 秒)
