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公开(公告)号：US5572159A
公开(公告)日：1996-11-05
申请号：US339328
申请日：1994-11-14
申请人： Harold L. McFarland
发明人： Harold L. McFarland
CPC分类号： G05F3/262 , G05F1/466 , H03K5/131 , H03K5/133 , H03K2005/00202
摘要： A voltage-controlled delay element utilizes a current-starved inverter configuration with a feedback path that ensures a rapid discharge of the storage node to ground once the desired delay time has elapsed. The circuit comprises a circuit path for charging the storage node (preferably rapidly), a first pull-down path capable of discharging the storage node at a rate determined by the control voltage, a second pull-down path capable of rapidly discharging the storage node, an output inverter, and a feedback connection between the output terminal of the output inverter and the second pull-down path to rapidly discharge the storage node when the output voltage starts rising. The circuit further comprises a means for programmably adjusting the delay in response to logic signals.
摘要翻译： 电压控制延迟元件利用具有反馈路径的电流饥饿逆变器配置，其确保一旦所需的延迟时间过去，存储节点快速放电到地面。 电路包括用于对存储节点（优选地快速）充电的电路，能够以由控制电压确定的速率对存储节点进行放电的第一下拉路径，能够快速地将存储节点放电的第二下拉路径 输出反相器和输出反相器的输出端子与第二下拉路径之间的反馈连接，以便在输出电压开始上升时快速放电存储节点。 电路还包括用于响应于逻辑信号可编程地调整延迟的装置。
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公开(公告)号：US5554949A
公开(公告)日：1996-09-10
申请号：US167265
申请日：1993-12-14
申请人： Thomas Suwald
发明人： Thomas Suwald
IPC分类号： G11C27/04 , G11C19/00 , H03H11/26 , H03K5/13 , H03K5/133 , H03K5/135 , H04N5/46 , H04N9/81 , H03K1/04 , H03K17/28
摘要： A circuit arrangement for delaying a useful signal which is stored in the form of time-discrete signal samples in a row of storage devices at time intervals which are determined by a clock signal and is read therefrom after expiration of a selectable delay time. Each storage device is connectable, via a respective input circuit to a useful signal input and, via a respective output circuit, to a useful signal output. The the input circuit of a storage device being activatable, together with the output circuit of the next storage device in the row, by a respective activation device, which includes a shift register device formed by a chain of bistable trigger circuits in which the output of each of the trigger circuits is connected to the input of the next trigger circuit in the chain, each activation device including one of the trigger circuits and all trigger circuits being switched by the clock signal, and also comprising a command device which applies a (first) start pulse to the first trigger circuit in the shift register device at a first instant and which enables the shift register device to propagate the start pulse through the chain of trigger circuits in conformity with the clock signal and which interrupts the propagation of the (first) start pulse at a second instant and at the same time applies a next start pulse to the first trigger circuit in the shift register device and enables the shift register device again to propagate said next start pulse, the time interval between the first instance (t1) and the second instant (t10) amounting to a selectable, integer multiple of periods of the clock signal, the number (n) of storage devices or trigger circuits corresponding at least to said multiple (n) of the periods of the clock signal. This circuit arrangement can be simply adapted to a plurality of different desired delay time values, during operation.
摘要翻译： 一种电路装置，用于以由时钟信号确定并且在可选择的延迟时间期满之后从其读取的时间间隔延迟以时间离散信号样本的形式存储在一行存储装置中的有用信号。 每个存储设备可通过相应的输入电路连接到有用的信号输入端，并经由相应的输出电路连接到有用的信号输出。 存储装置的输入电路可以通过相应的激活装置与可行的下一个存储装置的输出电路一起被激活，该激活装置包括由双稳态触发电路链形成的移位寄存器装置，其中输出 每个触发电路连接到链中的下一个触发电路的输入，每个激活装置包括触发电路中的一个并且所有触发电路都被时钟信号切换，并且还包括命令装置，其应用（第一 ）在第一时刻向移位寄存器装置中的第一触发电路启动脉冲，并且使得移位寄存器装置能够通过触发电路链传播起始脉冲，这与触发电路的时钟信号一致，并且中断了（第一 ）在第二时刻启动脉冲，并且同时将下一个起始脉冲施加到移位寄存器装置中的第一触发电路，并使能s 重新寄存装置传播下一个起始脉冲，时钟信号的周期的可选择的整数倍之间的时间间隔（t1）和第二时刻（t10）之间的时间间隔，存储装置的数量 或至少对应于时钟信号的所述多个（n）个周期的触发电路。 在操作期间，该电路装置可以简单地适应于多个不同的期望延迟时间值。
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公开(公告)号：US5369310A
公开(公告)日：1994-11-29
申请号：US891587
申请日：1992-06-01
申请人： Rajeev Badyal , Vernon Knowles
发明人： Rajeev Badyal , Vernon Knowles
CPC分类号： H03K17/223
摘要： A CMOS power-on reset circuit has a delay capacitor to provide a predetermined delay period. Charging and discharging of the delay capacitor is controlled by the state of a flipflop circuit. An input comparator monitors a power supply input voltage. An invalid input voltage level immediately changes the reset output signal to the invalid state and discharges the capacitor. Even after the input voltage has recovered to a valid level, recharging the capacitor is delayed until the capacitor has substantially discharged, thereby ensuring at least a predetermined delay period after the last fault condition. The delay capacitor is coupled in a feedback configuration so as to lower the threshold voltage when the delay capacitor voltage indicates to the valid state, to allow limited power supply sag, for example due to motor start-up, without resetting the circuit. Multiple power supply voltages are continuously monitored in a CMOS integrated configuration by additional input scaling resistor networks and input comparators, all coupled to the common 2-level threshold voltage node.
摘要翻译： CMOS上电复位电路具有延迟电容器以提供预定的延迟周期。 延迟电容器的充电和放电由触发器电路的状态控制。 输入比较器监视电源输入电压。 无效的输入电压电平立即将复位输出信号变为无效状态并对电容放电。 即使在输入电压恢复到有效电平之后，电容器的再充电被延迟直到电容器基本上放电，从而确保在最后的故障状态之后至少预定的延迟时间。 延迟电容器以反馈配置耦合，以便当延迟电容器电压指示为有效状态时降低阈值电压，以允许例如由于电动机起动而导致有限的电源暂降而不使电路复位。 多个电源电压通过附加的输入缩放电阻网络和输入比较器在CMOS集成配置中连续监控，全部耦合到公共2级阈值电压节点。
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公开(公告)号：US5329193A
公开(公告)日：1994-07-12
申请号：US974533
申请日：1992-11-12
申请人： Chao-Cheng Lu
发明人： Chao-Cheng Lu
IPC分类号： H03K17/732 , H03K17/28 , H03K5/24
CPC分类号： H03K17/732
摘要： A new computer controller is disclosed for controlling the output voltage of a SCR controller to a load. The computer controller includes a computer unit comprising a first pulse generator, a central processing unit, a first voltage comparator and a digital analog converter, and a control unit controlled by the computer unit and connected to the load through the SCR controller and consisting of a second pulse generator, an integrator circuit, a second voltage comparator, a turn-on circuit and a turn-off circuit.
摘要翻译： 公开了一种用于控制SCR控制器对负载的输出电压的新型计算机控制器。 计算机控制器包括计算机单元，其包括第一脉冲发生器，中央处理单元，第一电压比较器和数字模拟转换器，以及由计算机单元控制并通过SCR控制器连接到负载的控制单元， 第二脉冲发生器，积分器电路，第二电压比较器，导通电路和关断电路。
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45.发明授权
公开(公告)号：US5287023A
公开(公告)日：1994-02-15
申请号：US973575
申请日：1992-11-09
申请人： Tadashi Miyasaka
发明人： Tadashi Miyasaka
IPC分类号： H03K17/04 , H03K17/16 , H03K17/56 , H03K17/567 , H03K17/687 , H03K17/28
CPC分类号： H03K17/567 , H03K17/0406 , H03K17/163 , H03K17/168
摘要： In a reverse-bias control circuit for a voltage-driven switching element which turns on upon receiving a forward-bias voltage and turns off upon receiving a reverse-bias voltage, a step-down circuit is included which serves for stepping down a reverse-bias voltage after a time delay which is substantially equal to the turn-off delay of the voltage-driven switching element. The control circuit further includes a recovery circuit for stopping operation of the step-down circuit after a delay which is substantially equal to the total turn-off time of the voltage-driven switching element. The reverse-bias control circuit serves to reduce the reverse-bias voltage, thereby blocking surge-voltage disturbances, without increasing the turn-off delay time.
摘要翻译： 在用于电压驱动的开关元件的反向偏置控制电路中，其在接收到正向偏置电压时接通并在接收到反向偏置电压时截止，包括用于降压反向偏置电压的降压电路， 时间延迟之后的偏置电压基本上等于电压驱动的开关元件的关断延迟。 控制电路还包括恢复电路，用于在与电压驱动的开关元件的总关断时间基本相等的延迟之后停止降压电路的操作。 反向偏置控制电路用于减小反向偏置电压，从而阻止浪涌电压干扰，而不增加关断延迟时间。
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公开(公告)号：US5202800A
公开(公告)日：1993-04-13
申请号：US782248
申请日：1991-10-28
申请人： Philippe Perroud
发明人： Philippe Perroud
CPC分类号： G11B15/125 , G11B15/02
摘要： A device switches a coil (2) between a first state (REC) where it is connected between a supply source (V.sub.REC) and ground through a variable current source (I.sub.REC), and a second state (PB) where it is connected between ground and the input of an amplifier (3) through a coupling capacitor (CC). The device comprises a first controlled switch (T.sub.PB) connected in parallel to the current source (I.sub.REC); a second controlled switch (T.sub.REC) placed between the supply source (V.sub.REC) and the coil (2); a threshold comparator (4, V.sub.T), the inputs of which are connected across the capacitor (CC); a logic control circuit (5) receiving a state control signal (REC/PB) and the output signal (V.sub.C) of the threshold comparator (4, V.sub.T) and, as a function of these signals, alternatively controlling switches (T.sub.PB, T.sub.REC) with no overlapping of their closed states.
摘要翻译： 一种装置在线圈（2）之间通过可变电流源（IREC）将其连接在供电源（VREC）和接地之间的第一状态（REC）和在地之间连接的第二状态（PB） 以及通过耦合电容器（CC）的放大器（3）的输入。 该装置包括与电流源（IREC）并联连接的第一受控开关（TPB）; 放置在电源（VREC）和线圈（2）之间的第二受控开关（TREC）; 阈值比较器（4，VT），其输入端连接在电容器（CC）两端; 接收状态控制信号（REC / PB）和阈值比较器（4，VT）的输出信号（VC）的逻辑控制电路（5），并且作为这些信号的函数，交替地控制开关（TPB，TREC） 他们的封闭国家没有重叠。
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47.发明授权
公开(公告)号：US5124597A
公开(公告)日：1992-06-23
申请号：US678385
申请日：1991-04-01
CPC分类号： H03K5/133 , H03K2005/00156 , H03K2005/00163
摘要： A timer circuit provides a wide range of precise and substantially accurate time intervals. The timer circuit includes a ramp generator circuit having a first input for receiving an input signal to start a ramp signal, a second input for receiving a ramp timing conrol signal, and an output for providing a ramp signal. A comparator has a first input coupled to the output of the ramp generator, a second input coupled to a reference voltage source, and an output for providing an end ramp signal. A counter circuit has a first input for receiving the end ramp signal to begin counting, a second input for receiving a counter timing control signal, and an output for providing a terminal count signal. The end ramp signal and the terminal count signal are combined in an AND gate to provide a signal that is delayed by a predetermined amount from the input signal.
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公开(公告)号：US4925156A
公开(公告)日：1990-05-15
申请号：US279947
申请日：1988-12-05
申请人： Kurt Stoll , Hans H. Glattli
发明人： Kurt Stoll , Hans H. Glattli
CPC分类号： H03K17/64 , H01F7/1805 , H03K17/28
摘要： The invention provides a control circuit arrangement for solenoid valves, which has a timer adapted to supply the solenoid valve with a higher attraction current during an adjustable time starting with the beginning of a switching signal for the solenoid valve. After the time interval a low hold current flows until the end of the switching signal. For this purpose there is a semiconductor switch adapted to switch the flow of current through the solenoid valve. A logic gate arrangement is connected with an input of the switch and the gate arrangement is supplied with the output signal of the timer arranged to be triggered by the switching signal and the output signal of an oscillation generator. This circuit arrangement makes is possible to reduce a higher attraction current to a lower hold current in a simple and cheap manner, there only being a small overall size and as significant advantages it is possible for the arrangement to be converted for complementary logic.
摘要翻译： 本发明提供了一种用于电磁阀的控制电路装置，其具有定时器，其适于在从电磁阀的开关信号的开始开始的可调节时间期间向电磁阀提供较高的吸引电流。 在时间间隔之后，低电平保持电流流动直到开关信号的结束。 为此，存在适于切换电流通过电磁阀的电流的半导体开关。 逻辑门装置与开关的输入端连接，并且栅极装置被提供有定时器的输出信号，该输出信号被布置成由开关信号和振荡发生器的输出信号触发。 该电路装置可以以简单且便宜的方式将较高的吸引电流降低到较低的保持电流，只有较小的总体尺寸，并且显着的优点在于可将该装置转换为互补逻辑。
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49.发明授权
公开(公告)号：US4905199A
公开(公告)日：1990-02-27
申请号：US228587
申请日：1988-08-05
申请人： Takayuki Miyamoto
发明人： Takayuki Miyamoto
IPC分类号： H03K17/22 , G06F1/24 , G11C11/407 , G11C11/4074 , G11C11/4076 , G11C11/4078 , G11C11/409 , H03K17/28
CPC分类号： G11C11/4078 , G11C11/4074 , G11C11/4076
摘要： A circuit (50) is provided in a dynamic RAM (1) for detecting establishment of a substrate bias voltage (V.sub.BB) when the power is first turned on. A NAND gate (5d) in a clock generator circuit (10) immediately applies a high level signal to an inner circuit (11) when the power is turned on. Successively, the NAND gate (5d) applies a RAS signal to the inner circuit (11) in response to the establishment of V.sub.BB. Therefore, the dynamic RAM (1) is brought to a standby state immediately after the power is turned on and thereafter is controlled by the RAS signal. Consequently, flow of excessive current and latch-up immediately after the power is turned on can be prevented.
摘要翻译： 电源（50）设置在动态RAM（1）中，用于在电源首次接通时检测建立衬底偏置电压（VBB）。 当电源接通时，时钟发生器电路（10）中的与非门（5d）立即向内部电路（11）施加高电平信号。 接下来，NAND门（5d）响应于VBB的建立向内部电路（11）应用＆upbar＆R信号。 因此，动态RAM（1）在电源接通之后立即进入待机状态，此后由＆upbar＆R信号控制。 因此，可以防止在电源接通之后立即产生过大电流和闭锁的流动。
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50.发明授权
公开(公告)号：US4843253A
公开(公告)日：1989-06-27
申请号：US134308
申请日：1987-12-15
申请人： Vanni Poletto
发明人： Vanni Poletto
CPC分类号： H03K5/04 , H03K17/28 , H03K17/603
摘要： A circuit, which may be monolithically integrated, for the generation of current pulses of extremely short duration, includes a differential input structure with first and second PNP transistors. The circuit also includes third, fourth and fifth NPN transistors. The emitter of the third transistor is connected to the negative terminal of a supply voltage source via a first resistor, and to the emitter of the fourth transistor via a first diode and to the emitter of the fifth transistor via a second resistor. The collector of the third transistor is connected to the collector of the second transistor and to the base of the fifth transistor, via a second diode, and to the base of the fourth transistor. The base terminal of the third transistor is connected to the emitter of the fifth transistor via a third resistor and to the negative terminal of the supply voltage source via a capacitor. The collector of the fifth transistor is connected to the positive terminal of the supply voltage source. The collector of the fourth transistor is used as an output terminal of the circuit.
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