公开(公告)号：US5862068A

公开(公告)日：1999-01-19

申请号：US850820

申请日：1997-05-02

申请人： Takashi Onodera

发明人： Takashi Onodera

IPC分类号： G06F7/00 ,  G06F7/552 ,  G06F7/76 ,  G06F17/10 ,  H03F3/45 ,  G06F7/38

CPC分类号： G06F7/552 ,  G06F2207/5525 ,  G06F7/49942

摘要： An arithmetic circuit with a small number of parts performs high-speed arithmetic operations for calculating a square-root of a sum of squares of two numbers. Absolute values of two inputs S.sub.in1 and S.sub.in2 are determined by absolute value calculators and are compared by an absolute value comparator According to the comparison result, a first multiplexer selects the smaller of the two absolute values and a second multiplexer selects the larger of the two absolute values. The smaller absolute value is shifted by a 2-bit right shifter and by a 3-bit right shifter respectively, and the obtained shifted results are added together by a (N-2)-bit adder. The sum of the shifted values is then added by a N-bit adder to the larger absolute value. A square-root of the square-sum of two inputs S.sub.in1 and S.sub.in2 is thus approximately determined,

摘要翻译： 具有少量部件的算术电路执行用于计算两个数字的平方和的平方根的高速算术运算。 两个输入Sin1和Sin2的绝对值由绝对值计算器确定，并通过绝对值比较器进行比较根据比较结果，第一个多路复用器选择两个绝对值中较小的一个，第二个多路复用器选择两个绝对值中较大的绝对值 价值观。 较小的绝对值分别由2位右移位器和3位右移位器移位，并将获得的移位结果通过（N-2）位加法器相加在一起。 移位值的和然后由N位加法器加到较大的绝对值。 因此，近似地确定两个输入Sin1和Sin2的平方和的平方根，

公开(公告)号：US5787030A

公开(公告)日：1998-07-28

申请号：US498397

申请日：1995-07-05

申请人： J. Arjun Prabhu ,  Grzegorz B. Zyner

发明人： J. Arjun Prabhu ,  Grzegorz B. Zyner

IPC分类号： G06F7/537 ,  G06F7/00 ,  G06F7/483 ,  G06F7/506 ,  G06F7/52 ,  G06F7/535 ,  G06F7/552 ,  G06F7/76 ,  G06F7/38

CPC分类号： G06F7/535 ,  G06F7/5525 ,  G06F7/4873 ,  G06F7/49952

摘要： Quotient digit selection logic is modified so as to prevent a partial remainder equal to the negative divisor from occurring. An enhanced quotient digit selection function prevents the working partial remainder from becoming negative if the result is exact. The enhanced quotient digit selection logic chooses a quotient digit of zero instead of a quotient digit of one when the actual partial remainder is zero. Using a five bit estimated partial remainder where the upper four bits are zero, a possible carry propagation into fourth most significant bit is detected. This can be accomplished by looking at the fifth most significant sum and carry bits of the redundant partial remainder. If they are both zero, then a carry propagation out of that bit position into the least significant position of the estimated partial remainder is not possible, and a quotient digit of zero is chosen. In the alternative case in which one or both of the fifth most significant carry or sum bits of the redundant partial remainder are ones, a quotient digit of one is chosen. This provides a one cycle savings since negative partial remainders no longer need to be restored before calculating the sticky bit. Extra hardware is eliminated because it is no longer necessary to provide any extra mechanism for restoring the preliminary final partial remainder. Latency is improved because no additional cycle time is required to restore negative preliminary partial remainders. An optimized five-level circuit is shown which implements the enhanced quotient selection function.

摘要翻译： 修改商数字选择逻辑，以防止等于负除数的部分余数发生。 如果结果是精确的，增强的商数选择功能可防止工作部分余数变为负数。 当实际部分余数为零时，增强的商数选择逻辑选择零的商数，而不是1的商数。 使用五位估计的部分余数，其中高四位为零，检测到第四最高有效位的可能进位传播。 这可以通过查看第五最高有效和并且携带冗余部分余数的位来实现。 如果它们均为零，则从该位位置进入估计的部分余数的最低有效位置的进位传播是不可能的，并且选择零的商数。 在冗余部分余数的第五最高有效进位或和位中的一个或两个为一个的替代情况下，选择一个的商数。 这提供了一个周期的节省，因为在计算粘性位之前不再需要恢复负部分余数。 额外的硬件被消除，因为不再需要提供任何额外的机制来恢复初步的最终部分剩余。 改进了延迟，因为不需要额外的周期时间来恢复负的初步部分余数。 示出了优化的五电平电路，其实现增强的商选择功能。

公开(公告)号：US5726924A

公开(公告)日：1998-03-10

申请号：US680282

申请日：1996-07-11

申请人： John Michael Buss ,  James Douglas Dworkin ,  Scott Edward Lloyd ,  ShaoWei Pan ,  Stephen L. Smith ,  Shay-Ping Thomas Wang

发明人： John Michael Buss ,  James Douglas Dworkin ,  Scott Edward Lloyd ,  ShaoWei Pan ,  Stephen L. Smith ,  Shay-Ping Thomas Wang

IPC分类号： G06F7/552 ,  G06F7/556 ,  G06F1/02 ,  G06F7/00 ,  G06F7/50 ,  G06F15/00

CPC分类号： G06F7/556

摘要： A circuit and method for computing an exponential signal x.sup.g is provided. The circuit includes a logarithm converter which converts an input signal to binary word that represents the logarithm of an input signal x. A first shift register shifts the binary word in a bit-wise fashion to produce a first intermediate value; while a second shift register shifts the binary word in a bit-wise fashion to produce a second intermediate value. The shift registers may be implemented using multiplexers. The shifting operations are equivalent to multiplying the intermediate values by a factor which is a power of two. The first intermediate value is either added to or subtracted from the second intermediate value to produce a combined value. An inverse-logarithm converter converts the combined value to the exponential signal.

公开(公告)号：US5650953A

公开(公告)日：1997-07-22

申请号：US468186

申请日：1995-06-06

申请人： Takashi Kaku ,  Hideo Miyazawa

发明人： Takashi Kaku ,  Hideo Miyazawa

IPC分类号： H04L27/00 ,  G06F7/48 ,  G06F7/552 ,  G06F17/10 ,  H04M11/00

CPC分类号： G06F7/5525 ,  G06F17/10 ,  G06F7/4806 ,  G06F7/552 ,  G06F2207/5521 ,  G06F2207/5525

摘要： The level of the input vector signal (X+jY) is reduced to (X+jY)/.sqroot.2 in the overflow preventing circuit. A power arithmetic operating circuit squares the level-down input vector signal, to obtain a power value (X.sup.2 +Y.sup.2)/2. The initial value of the tap value (K) which is finally set to a reciprocal number value is multiplied two times by a multiplying circuit, thereby obtaining K.sup.2 (X+Y).sup.2 /2. Further, a differential circuit obtains an error signal (.DELTA.K)=1/2-K.sup.2 (X.sup.2 +Y.sup.2)/2 with a reference. An updating circuit updates the tap value (K) so that the error signal (.DELTA.K) is equal to 0. A loop arithmetic operation of the multiplication of the tap value, differential arithmetic operation, and updating of the tap value is repeated until the error signal (.DELTA.K) is converged to a predetermined value or less. The tap value (K) when it was converged is obtained as a reciprocal number value 1/.sqroot.(X.sup.2 +Y.sup.2) of the amplitude of the input vector signal.

摘要翻译： 在溢出防止电路中，输入矢量信号（X + jY）的电平减小到（X + jY）/ 2ROOT2。 功率算术运算电路使电平降低输入矢量信号平方，以获得功率值（X2 + Y2）/ 2。 将最终设定为倒数的抽头值（K）的初始值乘以乘法电路两次，从而得到K2（X + Y）2/2。 此外，差分电路获得参考的误差信号（DELTA K）= 1/2-K2（X2 + Y2）/ 2。 更新电路更新抽头值（K），使得误差信号（DELTA K）等于0.重复抽头值，微分算术运算和抽头值的更新的相乘的循环算术运算，直到 误差信号（DELTA K）收敛到预定值或更小。 获得收敛时的抽头值（K）作为输入矢量信号的幅度的倒数值1 / 2ROOT（X2 + Y2）。

公开(公告)号：US5646876A

公开(公告)日：1997-07-08

申请号：US424032

申请日：1995-04-18

申请人： Roger A. Smith

发明人： Roger A. Smith

IPC分类号： G06F7/552 ,  G06F7/38

CPC分类号： G06F7/552 ,  G06F2207/5523 ,  G06F7/483 ,  G06F7/49947

摘要： Rounding error can be reduced when evaluating binary floating point polynomials utilizing a Floating Point Unit (58) by first computing the sum of products of second and higher order polynomial terms. Next, the Floating Point Unit (58) adds a zero.sup.th level term to the product of a first order coefficient and an independent variable to form a "Big" term. The Floating Point Unit (58) calculates as a "Little" term the rounding error resulting from the computation of the "Big" term. The "Little" term is then added to the sum of products of higher order terms to form an "Intermediate" term. Finally, the Floating Point Unit (58) adds the "Big" term to the "Intermediate" term to form the polynomial result corrected by the rounding error introduced by the computation of the low order terms.

摘要翻译： 当使用浮点单元（58）评估二进制浮点多项式时，首先计算第二和更高阶多项式项的乘积之和，可以减少舍入误差。 接下来，浮点单元（58）将零级水平项添加到一阶系数和独立变量的乘积以形成“大”项。 浮点单元（58）计算出由“大”项计算产生的舍入误差的“小”项。 然后将“小”术语加到高阶项的总和中以形成“中级”术语。 最后，浮点单元（58）将“大”项添加到“中间”项，形成通过计算低阶项引入的舍入误差校正的多项式结果。

公开(公告)号：US5602768A

公开(公告)日：1997-02-11

申请号：US465992

申请日：1995-06-06

申请人： Walter B. Cunto ,  Jorge H. Goncalves

发明人： Walter B. Cunto ,  Jorge H. Goncalves

IPC分类号： G06F17/16 ,  G06F7/552 ,  G06F17/10

CPC分类号： G06F7/5525 ,  G06F17/10 ,  G06F2207/5523 ,  Y10S707/99937

摘要： The invention discloses a method and apparatus for solving a wide range of numerical problems that use N processing elements operating in parallel.To find the solution for a given problem relating to a given function function N points are selected in a determined interval wherein resides the solution. Such interval is known as the initial search interval and it is determined according to said given problem. Once the N points are selected the search interval is divided into smaller sub-intervals. The N processing elements are used to perform evaluations of the function at each of the N selected points, whereby the criteria for said evaluations are also determined according to said given problem. The results of the evaluations are used to determine the next search interval that is smaller than the previous one. The new search interval is divided into smaller parts in the same fashion as described above and further function evaluations are performed at given selected points. The aforementioned steps are repeated until the search interval is reduced to a predetermined size which is also defined according to said given problem. At this point the solution for said given problem can be selected from this last search interval known as the final interval.The apparatus for the present invention uses N processing elements operating in parallel to perform evaluations of the given function at selected points. When the invention is applied in digital computers for solving numerical problems involving a floating point domain, where points are represented by binary numbers according to a given pattern, selection of the N points in the search interval is implemented by a series of assemblers that build binary numbers.

摘要翻译： 本发明公开了一种用于解决使用并行操作的N个处理元件的广泛数值问题的方法和装置。 为了找到与给定功能函数相关的给定问题的解，在确定的间隔中选择N个点，其中驻留解决方案。 这种间隔被称为初始搜索间隔，并且根据所述给定的问题来确定。 一旦选择了N个点，搜索间隔被分成较小的子间隔。 N个处理元件用于对N个选择点中的每一个执行功能的评估，由此也可以根据所述给定的问题来确定所述评估的标准。 评估结果用于确定下一个小于前一个搜索间隔的搜索间隔。 以与上述相同的方式将新的搜索间隔分成较小的部分，并且在给定的选择点执行进一步的功能评估。 重复上述步骤，直到搜索间隔减小到也根据所述给定问题定义的预定大小。 此时，可以从称为最终间隔的最后一个搜索间隔中选择所述给定问题的解决方案。 用于本发明的装置使用并行操作的N个处理元件来在选定的点执行给定功能的评估。 当本发明应用于数字计算机中以解决涉及浮点域的数值问题时，其中点根据给定模式由二进制数表示，搜索间隔中的N个点的选择由构建二进制的一系列汇编器来实现 数字。

公开(公告)号：US5394350A

公开(公告)日：1995-02-28

申请号：US165322

申请日：1993-12-13

申请人： Jun-jin Gong ,  Hyun-woo Park ,  Hyun-gi Baek

发明人： Jun-jin Gong ,  Hyun-woo Park ,  Hyun-gi Baek

IPC分类号： G06F7/53 ,  G06F7/52 ,  G06F7/523 ,  G06F7/552 ,  H04L25/08

CPC分类号： G06F7/552 ,  G06F2207/5523

摘要： A square computation circuit outputs data of 4-bits to 12-bits by inputting the input data of 2-bits to 6-bits, respectively. The relationships between inputs and outputs are obtained and then simplified, which simplifies circuit configuration and increases processing speed, over the case of the square computation performed using a conventional multiplier.

摘要翻译： 平方计算电路通过分别输入2位至6位的输入数据来输出4位至12位的数据。 在使用常规乘法器进行的平方计算的情况下，获得输入和输出之间的关系，然后简化，这简化了电路配置并提高了处理速度。

公开(公告)号：US5341321A

公开(公告)日：1994-08-23

申请号：US058164

申请日：1993-05-05

申请人： Alan H. Karp ,  Peter Markstein ,  Dennis Brzezinski

发明人： Alan H. Karp ,  Peter Markstein ,  Dennis Brzezinski

IPC分类号： G06F7/483 ,  G06F7/52 ,  G06F7/527 ,  G06F7/535 ,  G06F7/552 ,  G06F7/38

CPC分类号： G06F7/535 ,  G06F7/5525 ,  G06F2207/382 ,  G06F2207/5355 ,  G06F2207/5356 ,  G06F7/4873 ,  G06F7/49936 ,  G06F7/49957

摘要： A floating point processing system which uses a multiplier unit and an adder unit to perform floating point division and square root operations using both a conventional and a modified form of the Newton-Raphson method. The modified form of the Newton-Raphson method is used in place of the final iteration of the conventional Newton-Raphson so as to compute high precision approximated results with a substantial improvement in speed. The invention computes approximated results faster and simplifies hardware requirements because no multiplications of numbers of the precision of the result are required.

摘要翻译： 一种浮点处理系统，其使用乘法器单元和加法器单元来使用牛顿 - 拉夫逊方法的常规和修改形式来执行浮点除法和平方根操作。 使用Newton-Raphson方法的修改形式来代替常规牛顿 - 拉夫森的最终迭代，以便计算出高精度近似结果，具有显着的速度提高。 本发明更快地计算近似结果并简化硬件要求，因为不需要对结果的精度数进行乘法运算。

公开(公告)号：US5305247A

公开(公告)日：1994-04-19

申请号：US956446

申请日：1992-10-02

申请人： Brett L. Lindsley

发明人： Brett L. Lindsley

IPC分类号： G06F7/52 ,  G06F7/535 ,  G06F7/552 ,  G06F7/38

CPC分类号： G06F7/535 ,  G06F7/5525 ,  G06F2207/5355 ,  G06F7/4873

摘要： A high-speed processor utilizes combinational logic and range limitation for a modified input value to increase efficiency in convergence factor determination for convergent division and square root computation. An input value is modified to a value in a limited range, which is then partitioned into two subdivisions. By utilizing these two groupings, the processing platform minimizes time consumption in conversion factor determination by inverting selected binary bits to form a modified factor and utilizes that modified factor to facilitate high-speed convergence factor computation.

摘要翻译： 高速处理器利用组合逻辑和范围限制修改输入值，以提高收敛因子确定中的收敛分割和平方根计算效率。 将输入值修改为有限范围内的值，然后将其分为两个细分。 通过利用这两个分组，处理平台通过反转所选二进制位来形成修正因子，最小化转换因子确定中的时间消耗，并利用该修正因子来促进高速收敛因子计算。

公开(公告)号：US5280439A

公开(公告)日：1994-01-18

申请号：US774674

申请日：1991-10-11

申请人： S. M. Quek ,  Larry Hu ,  Jnyaneshwar P. Prabhu ,  Frederick A. Ware

发明人： S. M. Quek ,  Larry Hu ,  Jnyaneshwar P. Prabhu ,  Frederick A. Ware

IPC分类号： G06F7/52 ,  G06F7/552 ,  G06F17/11

CPC分类号： G06F7/5338 ,  G06F17/11 ,  G06F7/535 ,  G06F7/552 ,  G06F7/5525 ,  G06F2207/382 ,  G06F2207/5355 ,  G06F2207/5356 ,  G06F2207/5521 ,  G06F2207/5523 ,  G06F7/4873 ,  G06F7/49957

摘要： In an apparatus and method for computing inverses and square roots, a highly accurate initial approximation is computed using a second order polynomial equation, the coefficients of which are stored in a ROM. The most significant bits of an operand are used to address a ROM to select coefficients, providing different coefficients for different operand ranges. The remaining lesser significant operand bits are used in the computation; the coefficient values already account for the bits used to address them. The result is in single precision accuracy. For double precision, the polynomial results are used as the first approximation for a Newton-Raphson iteration. The multiplier has a split array mode to speed up the calculation of the polynomial, whereby two lesser precision values can be computed at once. The size of the coefficients is tailored to produce the proper precision result for each of the elements of Ax.sup.2 +Bx+C. Separate values for the coefficients A, B, and C must be stored for the 1/x approximation and for the 1/.sqroot.x approximation. Also to speed up the multiplier, the multiplier can accept one operand in carry/save format, by providing Booth recoder logic which can accept operands in a normal binary or in a carry/save format. Also employed is a rounding technique which provides IEEE exact rounding by an operation that includes only one multiplication.

摘要翻译： 在用于计算反转和平方根的装置和方法中，使用二阶多项式方程来计算高精度的初始近似，其二次多项式方程存储在ROM中。 操作数的最高有效位用于寻址ROM以选择系数，为不同的操作数范围提供不同的系数。 其余较小的操作数位用于计算; 系数值已经是用于解决它们的位。 结果是单精度精度。 对于双精度，多项式结果被用作牛顿 - 拉夫逊迭代的第一近似。 乘法器具有分割阵列模式以加速多项式的计算，由此可以一次计算两个较小的精度值。 量化系数的大小，为Ax2 + Bx + C的每个元素产生适当的精度结果。 必须为1 / x近似和1 /（平方根）x近似存储系数A，B和C的单独值。 另外为了加快乘法器，乘法器可以通过提供可以以正常二进制或进位/保存格式接受操作数的Booth编码器逻辑，以进位/保存格式接受一个操作数。 同样采用的是舍入技术，其通过仅包括一个乘法的操作来提供IEEE精确舍入。