公开(公告)号：US5787030A

公开(公告)日：1998-07-28

申请号：US498397

申请日：1995-07-05

申请人： J. Arjun Prabhu ,  Grzegorz B. Zyner

发明人： J. Arjun Prabhu ,  Grzegorz B. Zyner

IPC分类号： G06F7/537 ,  G06F7/00 ,  G06F7/483 ,  G06F7/506 ,  G06F7/52 ,  G06F7/535 ,  G06F7/552 ,  G06F7/76 ,  G06F7/38

CPC分类号： G06F7/535 ,  G06F7/5525 ,  G06F7/4873 ,  G06F7/49952

摘要： Quotient digit selection logic is modified so as to prevent a partial remainder equal to the negative divisor from occurring. An enhanced quotient digit selection function prevents the working partial remainder from becoming negative if the result is exact. The enhanced quotient digit selection logic chooses a quotient digit of zero instead of a quotient digit of one when the actual partial remainder is zero. Using a five bit estimated partial remainder where the upper four bits are zero, a possible carry propagation into fourth most significant bit is detected. This can be accomplished by looking at the fifth most significant sum and carry bits of the redundant partial remainder. If they are both zero, then a carry propagation out of that bit position into the least significant position of the estimated partial remainder is not possible, and a quotient digit of zero is chosen. In the alternative case in which one or both of the fifth most significant carry or sum bits of the redundant partial remainder are ones, a quotient digit of one is chosen. This provides a one cycle savings since negative partial remainders no longer need to be restored before calculating the sticky bit. Extra hardware is eliminated because it is no longer necessary to provide any extra mechanism for restoring the preliminary final partial remainder. Latency is improved because no additional cycle time is required to restore negative preliminary partial remainders. An optimized five-level circuit is shown which implements the enhanced quotient selection function.

摘要翻译： 修改商数字选择逻辑，以防止等于负除数的部分余数发生。 如果结果是精确的，增强的商数选择功能可防止工作部分余数变为负数。 当实际部分余数为零时，增强的商数选择逻辑选择零的商数，而不是1的商数。 使用五位估计的部分余数，其中高四位为零，检测到第四最高有效位的可能进位传播。 这可以通过查看第五最高有效和并且携带冗余部分余数的位来实现。 如果它们均为零，则从该位位置进入估计的部分余数的最低有效位置的进位传播是不可能的，并且选择零的商数。 在冗余部分余数的第五最高有效进位或和位中的一个或两个为一个的替代情况下，选择一个的商数。 这提供了一个周期的节省，因为在计算粘性位之前不再需要恢复负部分余数。 额外的硬件被消除，因为不再需要提供任何额外的机制来恢复初步的最终部分剩余。 改进了延迟，因为不需要额外的周期时间来恢复负的初步部分余数。 示出了优化的五电平电路，其实现增强的商选择功能。

公开(公告)号：US5870323A

公开(公告)日：1999-02-09

申请号：US928073

申请日：1997-09-11

申请人： J. Arjun Prabhu ,  Grzegorz B. Zyner

发明人： J. Arjun Prabhu ,  Grzegorz B. Zyner

IPC分类号： G06F7/537 ,  G06F7/52 ,  G06F7/535 ,  G06F7/552 ,  G06F17/10

CPC分类号： G06F7/535 ,  G06F7/5525

摘要： In hardware SRT division and square root mantissa units maximal quotient selection overlapping for three quotient digits per cycle are used. An effective radix-8 implementation cascades three partial remainder computation circuits and overlaps three quotient selection circuits. Two carry save adders speculatively compute the possible resulting partial remainders corresponding to each possible value, -1, 0, and +1, of the quotient digit by adding the divisor, not adding anything, and adding the two's complement of the divisor, respectively, thus shortening the critical path of a single SRT iteration producing a single quotient digit. The propagation delays of two carry save adders which speculatively compute the possible resulting partial remainders are masked by a longer delay through quotient selection logic.

摘要翻译： 在硬件SRT划分和平方根尾数单位中，使用每个周期三个商数的最大商选择重叠。 有效的基数8实现级联三个部分余数计算电路并与三个商选择电路重叠。 两个进位保存加法器通过添加除数而不添加任何东西并分别添加除数的二进制补码来推测计算对应于商数的每个可能值-1,0和+1的可能的结果部分余数， 从而缩短产生单个商数的单个SRT迭代的关键路径。 推测计算可能产生的部分余数的两个进位保存加法器的传播延迟被商选择逻辑的较长延迟掩蔽。

公开(公告)号：US5696712A

公开(公告)日：1997-12-09

申请号：US498424

申请日：1995-07-05

申请人： J. Arjun Prabhu ,  Grzegorz B. Zyner

发明人： J. Arjun Prabhu ,  Grzegorz B. Zyner

IPC分类号： G06F7/537 ,  G06F7/52 ,  G06F7/535 ,  G06F7/552 ,  G06F17/10

CPC分类号： G06F7/535 ,  G06F7/5525

摘要： In hardware SRT division and square root mantissa units maximal quotient selection overlapping for three quotient digits per cycle are used. An effective radix-8 implementation cascades three partial remainder computation circuits and overlaps three quotient selection circuits. Two carry save adders speculatively compute the possible resulting partial remainders corresponding to each possible value, -1, 0 , and +1, of the quotient digit by adding the divisor, not adding anything, and adding the two's complement of the divisor, respectively, thus shortening the critical path of a single SRT iteration producing a single quotient digit. The propagation delays of two carry save adders which speculatively compute the possible resulting partial remainders are masked by a longer delay through quotient selection logic.

摘要翻译： 在硬件SRT划分和平方根尾数单位中，使用每个周期三个商数的最大商选择重叠。 有效的基数8实现级联三个部分余数计算电路并与三个商选择电路重叠。 两个进位保存加法器通过添加除数而不添加任何东西并分别添加除数的二进制补码来推测计算对应于商数的每个可能值-1,0和+1的可能的结果部分余数， 从而缩短产生单个商数的单个SRT迭代的关键路径。 推测计算可能产生的部分余数的两个进位保存加法器的传播延迟被商选择逻辑的较长延迟掩蔽。

公开(公告)号：US5671171A

公开(公告)日：1997-09-23

申请号：US498093

申请日：1995-07-05

申请人： Robert K. Yu ,  Grzegorz B. Zyner

发明人： Robert K. Yu ,  Grzegorz B. Zyner

IPC分类号： G06F7/57 ,  G06F7/52 ,  G06F7/552

CPC分类号： G06F7/483 ,  G06F7/49957

摘要： A floating point mantissa final addition and rounding unit uses a conditional sum adder to reduce a redundant carry-save format 106-bit mantissa to a non-redundant properly rounded 53-bit double-precision mantissa. The conditional sum adder simultaneously speculatively computes both the sum and the incremented sum of the upper 52 bits of the carry-save portions. A rounding unit speculatively computes the lower one bit and two bits of the mantissa for the cases of mantissa overflow or non-overflow, respectively. The rounding unit produces an overflow carry signal and a non-overflow carry signal. A multiplexor selects the proper 53 mantissa output bits from among the two conditional sum adder outputs and the rounding unit mantissa outputs depending upon the most significant bits of the two conditional sum adder outputs and the overflow and non-overflow carry signals. The floating point mantissa final addition and rounding unit is used to perform the final addition and rounding for a multiplier that produces a 106-bit carry-save result and for a division/square root unit that produces a 56-bit non-redundant result. A multiplexor selects the input from among the multiplier carry-save result and the division/square root unit non-redundant result. When the division/square root result is selected, the carry portion and the less significant 50 bits of the sum portion are set equal to zero. When a non-redundant result is input into the final addition and rounding unit, the conditional sum adder acts merely as an incrementer.

摘要翻译： 浮点尾数最后加法和舍入单元使用条件和加法器将冗余进位保存格式106位尾数减少到非冗余正确舍入的53位双精度尾数。 条件和加法器同时推测计算进位保存部分的高52位的和和加和和。 舍入单位推测性地计算尾数溢出或非溢出情况下尾数的下一位和两位。 舍入单元产生溢出进位信号和非溢出进位信号。 多路复用器根据两个条件和加法器输出的最高有效位和溢出和非溢出进位信号，从两个条件和加法器输出中选择合适的53尾数输出位和舍入单位尾数输出。 浮点尾数最后加法和舍入单位用于执行产生106位进位保存结果的乘法器的最终加法和舍入，以及产生56位非冗余结果的除法/平方根单位。 多路复用器从乘法器进位保存结果和除法/平方根单位非冗余结果中选择输入。 当选择除法/平方根结果时，总和部分的进位部分和较低有效的50位被设置为等于零。 当非冗余结果输入到最后的加法和舍入单元中时，条件和加法器仅作为增量器。

公开(公告)号：US6031992A

公开(公告)日：2000-02-29

申请号：US678541

申请日：1996-07-05

申请人： Robert F. Cmelik ,  David R. Ditzel ,  Edmund J. Kelly ,  Colin B. Hunter ,  Douglas A. Laird ,  Malcolm John Wing ,  Grzegorz B. Zyner

发明人： Robert F. Cmelik ,  David R. Ditzel ,  Edmund J. Kelly ,  Colin B. Hunter ,  Douglas A. Laird ,  Malcolm John Wing ,  Grzegorz B. Zyner

IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F9/455 ,  G06F9/45

CPC分类号： G06F9/3812 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/45504

摘要： A microprocessor for a host computer designed to execute target application programs for a target computer having a target instruction set including the combination of code morphing software, and morph host processing hardware designed to execute instructions of a host instruction set, the combination of the code morphing software and the morph host processing hardware comprising means to translate a set of target instructions into instructions of a host instruction set, means to optimize the instructions of the host instruction set translated from the target application program speculating upon the occurrence of a condition, means to determine under control of the code morphing software official state of the target computer which existed at the beginning of a translation of a set of target instructions during execution of the target application program by the microprocessor, means for updating state of the target computer from state of the host computer when a set of host instructions executes in accordance with the speculation, means to detect failure of the condition during the execution of the set of host instructions, means for updating state of the host computer from state of the target computer when a set of host instructions fails to execute in accordance with the speculation, and means to translate a new set of host instructions without the speculation when a set of host instructions fails to execute in accordance with the speculation.

摘要翻译： 一种用于主计算机的微处理器，被设计用于执行目标计算机的目标应用程序，所述目标计算机具有目标指令集，所述目标指令集包括代码变形软件的组合，以及被设计为执行主机指令集的指令的变形主机处理硬件，代码变形 软件和变形主机处理硬件包括将一组目标指令转换为主机指令集的指令的装置，用于优化从发生条件时推测的目标应用程序翻译的主机指令集的指令的装置， 在由微处理器在目标应用程序执行期间在一组目标指令的转换开始时存在的目标计算机的代码变形软件官方状态的控制下确定用于从目标计算机的状态更新目标计算机的状态的装置 主机当一套主机指令时 根据推测执行的装置，用于在执行主机指令集期间检测状况的失败的手段，用于当主机指令的集合根据不可执行的主机指令不能执行时从目标计算机的状态更新主机的状态的装置 当一组主机指令根据推测不能执行时，这种推测和翻译一组新的主机指令的手段无需推测。

公开(公告)号：US5619439A

公开(公告)日：1997-04-08

申请号：US498420

申请日：1995-07-05

申请人： Robert K. Yu ,  Grzegorz B. Zyner

发明人： Robert K. Yu ,  Grzegorz B. Zyner

IPC分类号： G06F7/57 ,  G06F7/38

CPC分类号： G06F7/483

摘要： The same hardware is used to implement calculations of the exponents for multiplication, division, and square root in either double or single precision. A multiplexor selects the appropriate bias value necessary for exponent computation for the given instruction type, operand precision, and output precision. A first operand multiplexor selects either the exponent of the first operand in the case of a multiplication or division instruction, and selects zero in the case of a square root instruction, since the square root operation only requires one operand. The second operand multiplexor selects the second exponent in the case of a multiplication instruction, the one's complement of the second exponent in the case of a division instruction, and the second exponent divided by two during a square root operation. Flip-flop registers latch the exponent and incremented exponent when a division or square root operation is pending. A multiplexor select between the presently calculated exponents and the saved exponents calculated for a pending division or square root operation. If the instruction scheduler has flexibility in allowing out of order instruction completion, younger multiplication instructions can be dispatched and completed during the several machine cycles during which the division/square root mantissa computation.

摘要翻译： 相同的硬件用于实现双精度或单精度乘法，除法和平方根的指数计算。 多路选择器为给定的指令类型，操作数精度和输出精度选择指数运算所需的适当偏置值。 在乘法或除法指令的情况下，第一个操作数复用器选择第一个操作数的指数，在平方根指令的情况下选择零，因为平方根操作只需要一个操作数。 在乘法指令的情况下，第二操作数复用器选择第二指数，在除法指令的情况下，第二指数的补码，以及平方根操作期间的第二指数除以2。 当分频或平方根操作挂起时，触发器寄存器将锁存指数和递增指数。 多路复用器在当前计算出的指数和为待分割或平方根操作计算的保存的指数之间进行选择。 如果指令调度器具有允许无序指令完成的灵活性，则可以在几个机器周期期间分派和完成较小的乘法指令，其中除法/平方根尾数计算。

公开(公告)号：US5150319A

公开(公告)日：1992-09-22

申请号：US695423

申请日：1991-05-03

申请人： Grzegorz B. Zyner

发明人： Grzegorz B. Zyner

IPC分类号： G06F7/38 ,  G06F7/487 ,  G06F7/506 ,  G06F7/52

CPC分类号： G06F7/4876 ,  G06F7/49915 ,  G06F7/49947

摘要： A rounding circuit for a binary tree floating point multiplier including apparatus for providing the upper bits of a mantissa presuming that no carry-in has occurred without waiting for the generation of a carry-in from lower order bits, apparatus for providing the upper bits of a mantissa presuming that a carry-in has occurred without waiting for the generation of a carry-in from lower order bits; apparatus for providing a first set of lower order bits for the mantissa based on an actual carry-in from a lower order bit adder and a rounding condition, the first set of lower order bits for the mantissa being chose for no mantissa overflow; apparatus for providing a second set of lower order bits for the mantissa based on an actual carry-in from a lower order bit adder and a rounding condition, the second set of lower order bits for the mantissa being chosen for mantissa overflow; and apparatus for selecting upper order bits and lower order bits for the mantissa based on whether a carry-in propagates past the lower order bits of the mantissa and whether a mantissa overflow has occurred.

公开(公告)号：US5072419A

公开(公告)日：1991-12-10

申请号：US616569

申请日：1990-11-21

申请人： Grzegorz B. Zyner

发明人： Grzegorz B. Zyner

IPC分类号： G06F7/509 ,  G06F7/52 ,  G06F7/53

CPC分类号： G06F7/5318

摘要： A binary integer multiplier including a plurality of adder stages, each of such adder stages including a plurality of cells equal to a number of bits in an operand, each of such adder stage including a pair of full adders capable of receiving six input bits and producing two result bits at the significance level of the cell and two carry bits at the next higher significance level, apparatus interconnecting the bits indicating partial products to the input terminals of a cell at each significance level, apparatus interconnecting the carry output terminals of a cell to input terminals of the cell at the next significance level, apparatus interconnecting one carry output terminal of a cell to any unused input terminal at a cell of a particular stage at which only three input signals are provided, and apparatus interconnecting the result terminals of each cell to the input terminals of the cell at the same significance level at the next adder level.

公开(公告)号：US07304969B2

公开(公告)日：2007-12-04

申请号：US11557728

申请日：2006-11-08

申请人： Philip J. Ryan ,  Andrew R. Adams ,  John D. O'Sullivan ,  Uri Parker ,  Brian Hart ,  Grzegorz B. Zyner

发明人： Philip J. Ryan ,  Andrew R. Adams ,  John D. O'Sullivan ,  Uri Parker ,  Brian Hart ,  Grzegorz B. Zyner

IPC分类号： H04Q7/00

CPC分类号： H03G3/3078

摘要： A digital AGC system for burst operation, particularly suited for receiving packets in a wireless local area network. One embodiment includes a log detector that provides a signal strength measure, called the received signal strength indication (RSSI) over a wide dynamic range. The AGC system includes estimating the power in a received signal by averaging the log of the signal power. The Start of Packet detection avoids using the radio receiver's main analog to digital converters to preserve power.

摘要翻译： 一种用于突发操作的数字AGC系统，特别适用于在无线局域网中接收分组。 一个实施例包括在宽动态范围内提供称为接收信号强度指示（RSSI）的信号强度测量的对数检测器。 AGC系统包括通过对信号功率的对数求平均来估计接收信号中的功率。 分组检测的开始避免使用无线电接收机的主要模数转换器来保持功率。

公开(公告)号：US07151759B1

公开(公告)日：2006-12-19

申请号：US10095668

申请日：2002-03-08

申请人： Philip J. Ryan ,  Andrew R. Adams ,  John D. O'Sullivan ,  Uri Parker ,  Brian Hart ,  Grzegorz B. Zyner

发明人： Philip J. Ryan ,  Andrew R. Adams ,  John D. O'Sullivan ,  Uri Parker ,  Brian Hart ,  Grzegorz B. Zyner

IPC分类号： H04Q7/00

CPC分类号： H03G3/3078

摘要： A digital AGC system for burst operation, particularly suited for receiving packets in a wireless local area network. One embodiment includes a log detector that provides a signal strength measure, called the received signal strength indication (RSSI) over a wide dynamic range. The AGC system includes estimating the power in a received signal by averaging the log of the signal power. The Start of Packet detection avoids using the radio receiver's main analog to digital converters to preserve power.

摘要翻译： 一种用于突发操作的数字AGC系统，特别适用于在无线局域网中接收分组。 一个实施例包括在宽动态范围内提供称为接收信号强度指示（RSSI）的信号强度测量的对数检测器。 AGC系统包括通过对信号功率的对数求平均来估计接收信号中的功率。 分组检测的开始避免使用无线电接收机的主要模数转换器来保持功率。