An arithmetic circuit with a small number of parts performs high-speed arithmetic operations for calculating a square-root of a sum of squares of two numbers. Absolute values of two inputs S.sub.in1 and S.sub.in2 are determined by absolute value calculators and are compared by an absolute value comparator According to the comparison result, a first multiplexer selects the smaller of the two absolute values and a second multiplexer selects the larger of the two absolute values. The smaller absolute value is shifted by a 2-bit right shifter and by a 3-bit right shifter respectively, and the obtained shifted results are added together by a (N-2)-bit adder. The sum of the shifted values is then added by a N-bit adder to the larger absolute value. A square-root of the square-sum of two inputs S.sub.in1 and S.sub.in2 is thus approximately determined,