公开(公告)号：US5640336A

公开(公告)日：1997-06-17

申请号：US581800

申请日：1996-01-02

申请人： James Douglas Dworkin ,  John Michael Buss

发明人： James Douglas Dworkin ,  John Michael Buss

IPC分类号： G06F7/552 ,  G06F7/38 ,  G06F7/52

CPC分类号： G06F7/552 ,  G06F2207/5523

摘要： A computational array (120) includes at least one computing element (130) that calculates multiple terms in a polynomial. The computing element (130) obtains an input value of each variable in each of the multiple terms and a subscript uniquely identifying the variable, The computing element (130) reads a term identifier and an exponent corresponding to the variable at a memory location based on the subscript, The computing element (130) multiplies the input value by a selected weight value and multiplies the input value by itself a number of times based on the exponent and stores the result at a memory location corresponding to the term identifier. The computing element (130) calculates multiple terms by distinguishing each of the terms with the term identifier.

摘要翻译： 计算阵列（120）包括计算多项式中的多个项的至少一个计算元件（130）。 计算元件（130）获得多个项中的每一个中的每个变量的输入值，以及唯一地标识变量的下标。计算元件（130）基于以下内容读取与存储器位置处的变量相对应的项目标识符和指数 下标，计算元件（130）将输入值乘以所选择的权重值，并且基于指数将输入值本身乘以多次，并将结果存储在与术语标识符相对应的存储器位置处。 计算元件（130）通过将每个术语与术语标识符区分开来计算多个术语。

公开(公告)号：US06356636B1

公开(公告)日：2002-03-12

申请号：US09120580

申请日：1998-07-22

申请人： Robert I. Foster ,  John Michael Buss ,  Rodney C. Tesch ,  James Douglas Dworkin ,  Michael J. Torla

发明人： Robert I. Foster ,  John Michael Buss ,  Rodney C. Tesch ,  James Douglas Dworkin ,  Michael J. Torla

IPC分类号： H04L930

CPC分类号： G06F7/728

摘要： A co-processor (44) executes a mathematical algorithm that computes modular exponentiation equations for encrypting or decrypting data. A pipelined multiplier (56) receives sixteen bit data values stored in an A/B RAM (72) and generates a partial product. The generated partial product is summed in an adder (58) with a previous partial product stored in a product RAM (64). A modulo reducer (60) causes a binary data value N to be aligned and added to the summed value when a particular data bit location of the summed value has a logic one value. An N RAM (70) stores the data value N that is added in a modulo reducer (60) to the summed value. The co-processor (44) computes the Foster-Montgomery Reduction Algorithm and reduces the value of (A*B mod N) without having to first compute the value of &mgr; as is required in the Montgomery Reduction Algorithm.

摘要翻译： 协处理器（44）执行计算用于加密或解密数据的模幂等式的数学算法。 流水线乘法器（56）接收存储在A / B RAM（72）中的16位数据值，并产生部分乘积。 所产生的部分乘积在加法器（58）中与先前的部分乘积存储在乘积RAM（64）中相加。 当求和值的特定数据位位置具有逻辑1值时，模减法器（60）使二进制数据值N对齐并相加到求和值。 N RAM（70）将在模减法器（60）中添加的数据值N存储到求和值。 协处理器（44）计算福斯特蒙哥马利削减算法，并且减少（A * B mod N）的值，而不必首先按照Montgomery Reduction算法的要求计算mu的值。

公开(公告)号：US06259720B1

公开(公告)日：2001-07-10

申请号：US08764344

申请日：1996-12-12

申请人： John Michael Buss ,  James Douglas Dworkin ,  Stephen Lee Smith

发明人： John Michael Buss ,  James Douglas Dworkin ,  Stephen Lee Smith

IPC分类号： H04B169

CPC分类号： H04B1/707 ,  H04B1/7103 ,  H04B1/7115 ,  H04B2201/7071

摘要： A programmable versatile digital signal processing system architecture (FIG. 5) allows the implementation of functions for transmitting and receiving a variety of narrow and wide-band communication signaling schemes. The flexibility of the architecture (FIG. 5) makes it possible to receive and transmit many different spectral communication signals in real time by implementing signal processing functions such as filtering, spreading, de-spreading, rake filtering, and equalization under the direction of program instructions (FIGS. 13, 14, 15, and 16).

摘要翻译： 可编程通用数字信号处理系统架构（图5）允许实现用于发送和接收各种窄带和宽带通信信令方案的功能。 架构的灵活性（图5）使得可以通过在程序的方向上实现诸如滤波，扩展，解扩，耙滤波和均衡之类的信号处理功能来实时地接收和发送许多不同的频谱通信信号 指令（图13，图14，图15和图16）。

公开(公告)号：US06182104B2

公开(公告)日：2001-01-30

申请号：US09120835

申请日：1998-07-22

申请人： Robert I. Foster ,  John Michael Buss ,  Rodney C. Tesch ,  James Douglas Dworkin ,  Michael J. Torla

发明人： Robert I. Foster ,  John Michael Buss ,  Rodney C. Tesch ,  James Douglas Dworkin ,  Michael J. Torla

IPC分类号： G06F738

CPC分类号： G06F7/728

摘要： A co-processor (44) executes a mathematical algorithm that computes modular exponentiation equations for encrypting or decrypting data. A pipelined multiplier (56) receives sixteen bit data values stored in an A/B RAM (72) and generates a partial product. The generated partial product is summed in a summer (58) with a previous partial product stored in a product RAM (64). A modulo reducer (60) causes a binary data value N to be aligned and added to the summed value when a particular data bit location of the summed value has a logic one value. An N RAM (70) stores the data value N that is added in a modulo reducer (60) to the summed value. The co-processor (44) computes the Foster-Montgomery Reduction Algorithm and reduces the value of (A*B mod N) without having to first compute the value of &mgr; as is required in the Montgomery Reduction Algorithm.

摘要翻译： 协处理器（44）执行计算用于加密或解密数据的模幂等式的数学算法。 流水线乘法器（56）接收存储在A / B RAM（72）中的16位数据值，并产生部分乘积。 生成的部分乘积在夏季（58）中与先前的部分积存在产品RAM（64）中相加。 当求和值的特定数据位位置具有逻辑1值时，模减法器（60）使二进制数据值N对齐并相加到求和值。 N RAM（70）将在模减法器（60）中添加的数据值N存储到求和值。 协处理器（44）计算福斯特蒙哥马利削减算法，并且减少（A * B mod N）的值，而不必首先按照Montgomery Reduction算法的要求计算mu的值。

公开(公告)号：US5726924A

公开(公告)日：1998-03-10

申请号：US680282

申请日：1996-07-11

申请人： John Michael Buss ,  James Douglas Dworkin ,  Scott Edward Lloyd ,  ShaoWei Pan ,  Stephen L. Smith ,  Shay-Ping Thomas Wang

发明人： John Michael Buss ,  James Douglas Dworkin ,  Scott Edward Lloyd ,  ShaoWei Pan ,  Stephen L. Smith ,  Shay-Ping Thomas Wang

IPC分类号： G06F7/552 ,  G06F7/556 ,  G06F1/02 ,  G06F7/00 ,  G06F7/50 ,  G06F15/00

CPC分类号： G06F7/556

摘要： A circuit and method for computing an exponential signal x.sup.g is provided. The circuit includes a logarithm converter which converts an input signal to binary word that represents the logarithm of an input signal x. A first shift register shifts the binary word in a bit-wise fashion to produce a first intermediate value; while a second shift register shifts the binary word in a bit-wise fashion to produce a second intermediate value. The shift registers may be implemented using multiplexers. The shifting operations are equivalent to multiplying the intermediate values by a factor which is a power of two. The first intermediate value is either added to or subtracted from the second intermediate value to produce a combined value. An inverse-logarithm converter converts the combined value to the exponential signal.

公开(公告)号：US5852730A

公开(公告)日：1998-12-22

申请号：US764429

申请日：1996-12-12

申请人： John Michael Buss ,  James Douglas Dworkin ,  Stephen Lee Smith

发明人： John Michael Buss ,  James Douglas Dworkin ,  Stephen Lee Smith

IPC分类号： H03H17/04 ,  H03H17/06 ,  H04B1/707 ,  H04B1/7103 ,  H04B1/7115 ,  G06F9/40

CPC分类号： H04B1/707 ,  H04B1/7103 ,  H04B1/7115 ,  H04B2201/7071

摘要： A programmable versatile digital signal processing system architecture (FIG. 5) allows the implementation of functions for transmitting and receiving a variety of narrow and wide-band communication signaling schemes. The flexibility of the architecture (FIG. 5) makes it possible to receive and transmit many different spectral communication signals in real time by implementing signal processing functions such as filtering, spreading, de-spreading, rake filtering, and equalization under the direction of program instructions (1300, 1400, 1500, 1600).

摘要翻译： 可编程通用数字信号处理系统架构（图5）允许实现用于发送和接收各种窄带和宽带通信信令方案的功能。 架构的灵活性（图5）使得可以通过在程序的方向上实现诸如滤波，扩展，解扩，耙滤波和均衡之类的信号处理功能来实时地接收和发送许多不同的频谱通信信号 说明书（1300,1400,1500,1600）。