发明授权
US5646876A Method and apparatus for reducing rounding error when evaluating binary floating point polynomials 失效
评估二进制浮点多项式时减少舍入误差的方法和装置

  • 专利标题: Method and apparatus for reducing rounding error when evaluating binary floating point polynomials
  • 专利标题(中): 评估二进制浮点多项式时减少舍入误差的方法和装置
  • 申请号: US424032
    申请日: 1995-04-18
  • 公开(公告)号: US5646876A
    公开(公告)日: 1997-07-08
  • 发明人: Roger A. Smith
  • 申请人: Roger A. Smith
  • 申请人地址: IL Schaumburg
  • 专利权人: Motorola, Inc.
  • 当前专利权人: Motorola, Inc.
  • 当前专利权人地址: IL Schaumburg
  • 主分类号: G06F7/552
  • IPC分类号: G06F7/552 G06F7/38
Method and apparatus for reducing rounding error when evaluating binary
floating point polynomials
摘要:
Rounding error can be reduced when evaluating binary floating point polynomials utilizing a Floating Point Unit (58) by first computing the sum of products of second and higher order polynomial terms. Next, the Floating Point Unit (58) adds a zero.sup.th level term to the product of a first order coefficient and an independent variable to form a "Big" term. The Floating Point Unit (58) calculates as a "Little" term the rounding error resulting from the computation of the "Big" term. The "Little" term is then added to the sum of products of higher order terms to form an "Intermediate" term. Finally, the Floating Point Unit (58) adds the "Big" term to the "Intermediate" term to form the polynomial result corrected by the rounding error introduced by the computation of the low order terms.
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