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公开(公告)号：US10812400B2
公开(公告)日：2020-10-20
申请号：US15870974
申请日：2018-01-14
发明人： Andrew Edwards , Martin Ross
IPC分类号： H04L12/841 , G06F5/06 , H04L29/08 , H04L29/06
摘要： A method for configuring an adaptable circuit breaker chain in a microservices architecture includes transmitting a request from an upstream service to a target one of the services and receiving in a circuit breaker of the upstream service a response from a circuit breaker of the target indicating an inability to provide a response to the transmitted request and including meta-data describing an attempt by the circuit breaker of the target to receive a response from the downstream service to an underlying request of the target necessary to provide a response to the request transmitted by the upstream service. Finally, on condition that the meta-data indicates a delay by the circuit breaker of the target incurred in receiving a response to the underlying request, the method includes changing a pattern of delay imposed by the circuit breaker of the upstream service from a default pattern of delay.
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公开(公告)号：US10783216B2
公开(公告)日：2020-09-22
申请号：US16139339
申请日：2018-09-24
摘要： Various embodiments of the present technology may comprise a method and apparatus for in-place fast Fourier transform (FFT). According to various embodiments, the apparatus comprises a RAM, having a single address space, divided into a plurality of sub-memory spaces, where the number of sub-memory spaces is a function of a length of the FFT such that the two inputs are always from different sub-memories, as are the two outputs. According to various embodiments, the apparatus may further comprise a division circuit configured to perform a “bitwise” division operation in order to convert addresses from the aforementioned single address space to the particular sub-memories and addresses within them. According to various embodiments, the apparatus may further comprise a butterfly processor capable of performing a butterfly operation.
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公开(公告)号：US10769070B2
公开(公告)日：2020-09-08
申请号：US16140625
申请日：2018-09-25
申请人： Arm Limited
发明人： Joseph Michael Pusdesris , Miles Robert Dooley , Alexander Cole Shulyak , Krishnendra Nathella , Dam Sunwoo
IPC分类号： G06F12/0862 , G06F9/30 , G06F5/06
摘要： Apparatuses and methods for prefetch generation are disclosed. Prefetching circuitry receives addresses specified by load instructions and can cause retrieval of a data value from an address before that address is received. Stride determination circuitry determines stride values as a difference between a current address and a previously received address. Plural stride values corresponding to a sequence of received addresses are determined. Multiple stride storage circuitry stores the plurality of stride values determined by the stride determination circuitry. New address comparison circuitry determines whether a current address corresponds to a matching stride value based on the plurality of stride values stored in the multiple stride storage circuitry. Prefetch initiation circuitry can causes a data value to be retrieved from a further address, wherein the further address is the current address modified by the matching stride value of the plurality of stride values. By the use of multiple stride values, more complex load address patterns can be prefetched.
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公开(公告)号：US20200278837A1
公开(公告)日：2020-09-03
申请号：US16649948
申请日：2018-11-05
摘要： An adder circuit inhibiting overflow is provided. A first memory, a second memory, a third memory, and a fourth memory are included. A step of supplying first data with a sign to the first memory and supplying the first data with a positive sign stored in the first memory, to the second memory; a step of supplying the first data with a negative sign stored in the second memory, to the third memory; a step of generating second data by adding the first data with a positive sign stored in the second memory and the first data with a negative sign stored in the third memory; and a step of storing the second data in the fourth memory are included. When the second data stored in the fourth memory are all second data with a positive sign or all second data with a negative sign, all the second data stored in the fourth memory are added.
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公开(公告)号：US10761587B2
公开(公告)日：2020-09-01
申请号：US16193247
申请日：2018-11-16
申请人： RAMBUS INC.
IPC分类号： G06F1/324 , G11C7/10 , G11C7/22 , G11C11/4093 , G11C11/4076 , G06F1/3234 , G06F1/3287 , G06F5/06 , G11C7/04 , H03L7/081
摘要： Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
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公开(公告)号：US10754801B2
公开(公告)日：2020-08-25
申请号：US16846146
申请日：2020-04-10
IPC分类号： G11C5/14 , G06F13/16 , G06F1/3206 , G06F5/06 , G06F1/3296 , G06F1/3234
摘要： Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.
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47.发明申请公开(公告)号：US20200257467A1
公开(公告)日：2020-08-13
申请号：US16778578
申请日：2020-01-31
申请人： quadric.io, Inc.
IPC分类号： G06F3/06 , G06F5/06 , G06N3/04 , G06F9/30 , G06F12/1027
摘要： A system and method for random access augmented flow-based processing within an integrated circuit includes computing, by a plurality of distinct processing cores, a plurality of linear indices and associated valid bits; propagating the plurality of linear indices in a predetermined manner to a plurality of columns of first-in, first-out buffers; loading, from the FIFO buffers, the plurality of linear indices to a content addressable memory; at the CAM: coalescing redundant linear indices in each of the plurality of FIFO buffers; performing lookups for a plurality of memory addresses based on the plurality of linear indices; collecting at a read data buffer a plurality of distinct pieces of data from one of an on-chip memory based on the plurality of memory addresses; reading the plurality of distinct pieces of data from the read data buffer; and propagating the plurality of distinct pieces of data into the processing cores.
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公开(公告)号：US20200244274A1
公开(公告)日：2020-07-30
申请号：US16261161
申请日：2019-01-29
发明人： Visvesh S. Sathe
摘要： A control circuit includes a digital load, a voltage conversion circuit configured to provide a supply voltage to the digital load, an oscillator configured to provide, to the digital load, a clock signal having an oscillation frequency that (i) depends on the supply voltage and (ii) is less than a reciprocal of a critical path delay of the digital load, and a phase detector configured to provide, to the voltage conversion circuit, a phase signal that is indicative of a phase difference between the clock signal and a reference signal. The voltage conversion circuit is further configured to adjust the supply voltage based on the phase signal such that the oscillator changes the oscillation frequency to reduce the phase difference.
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49.发明申请公开(公告)号：US20200226473A1
公开(公告)日：2020-07-16
申请号：US16744039
申请日：2020-01-15
发明人： Hardik Sharma , Jongse Park
摘要： For one embodiment, a hardware accelerator with a heterogeneous-precision architecture for training quantized neural networks is described. In one example, a hardware accelerator for training quantized neural networks comprises a multilevel memory to store data and a software controllable mixed precision array coupled to the memory. The mixed precision array includes an input buffer, detect logic to detect zero value operands, and a plurality of heterogenous precision compute units to perform computations of mixed precision data types for the forward and backward propagation phase of training quantized neural networks.
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公开(公告)号：US10698851B1
公开(公告)日：2020-06-30
申请号：US16366139
申请日：2019-03-27
发明人： Kai-Ting Shr , Chia-Wei Yu
摘要： A data bit width converter is adapted to: convert first data using a first bit width as a data segment unit and second data using a second bit width as a data segment unit, and provide a cache to temporarily store third data, wherein the first bit width is not equal to the second bit width. The data bit width converter includes a slave, a cache, and a data reconstitution circuit. The slave is configured to read and write the second data. The cache is configured to read and write the third data. The data reconstitution circuit is configured to: convert the first data and the second data, and sequentially search the cache and the slave for the second data according to a searching program, to output the first data, and write the third data to the cache according to a temporary storage program.
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