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公开(公告)号：US10783216B2
公开(公告)日：2020-09-22
申请号：US16139339
申请日：2018-09-24
摘要： Various embodiments of the present technology may comprise a method and apparatus for in-place fast Fourier transform (FFT). According to various embodiments, the apparatus comprises a RAM, having a single address space, divided into a plurality of sub-memory spaces, where the number of sub-memory spaces is a function of a length of the FFT such that the two inputs are always from different sub-memories, as are the two outputs. According to various embodiments, the apparatus may further comprise a division circuit configured to perform a “bitwise” division operation in order to convert addresses from the aforementioned single address space to the particular sub-memories and addresses within them. According to various embodiments, the apparatus may further comprise a butterfly processor capable of performing a butterfly operation.
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公开(公告)号：US20200097519A1
公开(公告)日：2020-03-26
申请号：US16139339
申请日：2018-09-24
摘要： Various embodiments of the present technology may comprise a method and apparatus for in-place fast Fourier transform (FFT). According to various embodiments, the apparatus comprises a RAM, having a single address space, divided into a plurality of sub-memory spaces, where the number of sub-memory spaces is a function of a length of the FFT such that the two inputs are always from different sub-memories, as are the two outputs. According to various embodiments, the apparatus may further comprise a division circuit configured to perform a “bitwise” division operation in order to convert addresses from the aforementioned single address space to the particular sub-memories and addresses within them. According to various embodiments, the apparatus may further comprise a butterfly processor capable of performing a butterfly operation.
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公开(公告)号：US12067696B2
公开(公告)日：2024-08-20
申请号：US17647870
申请日：2022-01-13
IPC分类号： G06T3/4092 , H01L27/146 , H04N23/45 , H04N25/44
CPC分类号： G06T3/4092 , H04N23/45 , H04N25/44 , H01L27/14609
摘要： A system is provided that is configured to encode an image in accordance with a variable resolution image format. The variable resolution image format allows the specification of a number of windows in terms of their location and resolution. The image can be decomposed into a minimum number of square superpixels such that all specified windows are at the assigned resolution or better. By encoding one image where only critical portions are at the high resolution while less critical portions are at intermediate or lower resolutions, the number of bits that need to be transmitted from the system to a remote host subsystem can be dramatically reduced.
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公开(公告)号：US11609539B2
公开(公告)日：2023-03-21
申请号：US16742259
申请日：2020-01-14
IPC分类号： G01S17/10 , G04F10/00 , G01S7/4861
摘要： Various embodiments of the present technology may provide methods and apparatus for a time-to-digital converter. The time-to-digital converter may include a state machine that increments/decrements according to an input signal and a count value. The time-to-digital converter may further include a register to store the count value according to the input signal.
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