公开(公告)号：US11294828B2

公开(公告)日：2022-04-05

申请号：US16412674

申请日：2019-05-15

申请人： Arm Limited

发明人： Jaekyu Lee ,  Dam Sunwoo

IPC分类号： G06F12/12 ,  G06F9/38 ,  G06F12/0862

摘要： An apparatus and method are provided for controlling allocation of information into a cache storage. The apparatus has processing circuitry for executing instructions, and for allowing speculative execution of one or more of those instructions. A cache storage is also provided having a plurality of entries to store information for reference by the processing circuitry, and cache control circuitry is used to control the cache storage, the cache control circuitry comprising a speculative allocation tracker having a plurality of tracking entries. The cache control circuitry is responsive to a speculative request associated with the speculative execution, requiring identified information to be allocated into a given entry of the cache storage, to allocate a tracking entry in the speculative allocation tracker for the speculative request before allowing the identified information to be allocated into the given entry of the cache storage. The allocated tracking entry is employed to maintain restore information sufficient to enable the given entry to be restored to an original state that existed prior to the identified information being allocated into the given entry. The cache control circuitry is further responsive to a mis-speculation condition being detected in respect of the speculative request, to employ the restore information maintained in the allocated tracking entry for that speculative request in order to restore the given entry in the cache storage to the original state. Such an approach can provide robust protection against speculation-based cache timing side-channel attacks whilst alleviating the performance and/or power consumption issues associated with known techniques.

公开(公告)号：US20200097409A1

公开(公告)日：2020-03-26

申请号：US16139160

申请日：2018-09-24

申请人： Arm Limited

发明人： Krishnendra Nathella ,  Chris Abernathy ,  Huzefa Moiz Sanjeliwala ,  Dam Sunwoo ,  Balaji Vijayan

IPC分类号： G06F12/0862 ,  G06F9/30

摘要： A variety of data processing apparatuses are provided in which stride determination circuitry determines a stride value as a difference between a current address and a previously received address. Stride storage circuitry stores an association between stride values determined by the stride determination circuitry and a frequency during a training period. Prefetch circuitry causes a further data value to be proactively retrieved from a further address. The further address is the current address modified by a stride value in the stride storage circuitry having a highest frequency during the training period. The variety of data processing apparatuses are directed towards improving efficiency by variously disregarding certain candidate stride values, considering additional further addresses for prefetching by using multiple stride values, using feedback to adjust the training process and compensating for page table boundaries.

公开(公告)号：US11640381B2

公开(公告)日：2023-05-02

申请号：US16519498

申请日：2019-07-23

申请人： Arm Limited

发明人： Gwangsun Kim ,  Dam Sunwoo

IPC分类号： G06F16/22

摘要： Briefly, example methods, apparatuses, devices, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more processing devices to facilitate and/or support one or more operations and/or techniques to access entries in a hash table. In a particular implementation, a hash operation may be selected from between or among multiple hash operations to map key values to entries in a hash table.

公开(公告)号：US11599361B2

公开(公告)日：2023-03-07

申请号：US17315737

申请日：2021-05-10

申请人： Arm Limited

发明人： Jaekyu Lee ,  Yasuo Ishii ,  Krishnendra Nathella ,  Dam Sunwoo

IPC分类号： G06F9/38

摘要： A data processing apparatus is provided. It includes control flow detection prediction circuitry that performs a presence prediction of whether a block of instructions contains a control flow instruction. A fetch queue stores, in association with prediction information, a queue of indications of the instructions and the prediction information comprises the presence prediction. An instruction cache stores fetched instructions that have been fetched according to the fetch queue. Post-fetch correction circuitry receives the fetched instructions prior to the fetched instructions being received by decode circuitry, the post-fetch correction circuitry includes analysis circuitry that causes the fetch queue to be at least partly flushed in dependence on a type of a given fetched instruction and the prediction information associated with the given fetched instruction.

公开(公告)号：US11966785B2

公开(公告)日：2024-04-23

申请号：US16943117

申请日：2020-07-30

申请人： Arm Limited

发明人： Dam Sunwoo ,  Supreet Jeloka ,  Saurabh Pijuskumar Sinha ,  Jaekyu Lee ,  Jose Alberto Joao ,  Krishnendra Nathella

IPC分类号： G06F9/46 ,  G06F9/50 ,  G06N5/04 ,  G06N20/00

CPC分类号： G06F9/5044 ,  G06F9/5038 ,  G06F9/505 ,  G06N5/04 ,  G06N20/00

摘要： A method for controlling hardware resource configuration for a processing system comprises obtaining performance monitoring data indicative of processing performance associated with workloads to be executed on the processing system, providing a trained machine learning model with input data depending on the performance monitoring data; and based on an inference made from the input data by the trained machine learning model, setting control information for configuring the processing system to control an amount of hardware resource allocated for use by at least one processor core. A corresponding method of training the model is provided. This is particularly useful for controlling inter-core borrowing of resource between processor cores in a multi-core processing system, where resource is borrowed between respective cores, e.g. cores on different layers of a 3D integrated circuit.

公开(公告)号：US10769070B2

公开(公告)日：2020-09-08

申请号：US16140625

申请日：2018-09-25

申请人： Arm Limited

发明人： Joseph Michael Pusdesris ,  Miles Robert Dooley ,  Alexander Cole Shulyak ,  Krishnendra Nathella ,  Dam Sunwoo

IPC分类号： G06F12/0862 ,  G06F9/30 ,  G06F5/06

摘要： Apparatuses and methods for prefetch generation are disclosed. Prefetching circuitry receives addresses specified by load instructions and can cause retrieval of a data value from an address before that address is received. Stride determination circuitry determines stride values as a difference between a current address and a previously received address. Plural stride values corresponding to a sequence of received addresses are determined. Multiple stride storage circuitry stores the plurality of stride values determined by the stride determination circuitry. New address comparison circuitry determines whether a current address corresponds to a matching stride value based on the plurality of stride values stored in the multiple stride storage circuitry. Prefetch initiation circuitry can causes a data value to be retrieved from a further address, wherein the further address is the current address modified by the matching stride value of the plurality of stride values. By the use of multiple stride values, more complex load address patterns can be prefetched.

公开(公告)号：US20230029860A1

公开(公告)日：2023-02-02

申请号：US17388927

申请日：2021-07-29

申请人： Arm Limited

发明人： Joshua Randall ,  Alejandro Rico Carro ,  Dam Sunwoo ,  Saurabh Pijuskumar Sinha ,  Jamshed Jalal

IPC分类号： G06F12/0811 ,  G06F12/084 ,  G06F12/0813 ,  H04L12/933 ,  H04L12/717

摘要： Various implementations described herein are directed to a device with a multi-layered logic structure with multiple layers including a first layer and a second layer arranged vertically in a stacked configuration. The device may have a first cache memory with first interconnect logic disposed in the first layer. The device may have a second cache memory with second interconnect logic disposed in the second layer, wherein the second interconnect logic in the second layer is linked to the first interconnect logic in the first layer.

公开(公告)号：US11526356B2

公开(公告)日：2022-12-13

申请号：US16887442

申请日：2020-05-29

申请人： Arm Limited

发明人： Lingzhe Cai ,  Krishnendra Nathella ,  Jaekyu Lee ,  Dam Sunwoo

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/54 ,  G06F12/0862 ,  G06F12/1027 ,  G06F9/52

摘要： An apparatus and method is provided, the apparatus comprising a processor pipeline to execute instructions, a cache structure to store information for reference by the processor pipeline when executing said instructions; and prefetch circuitry to issue prefetch requests to the cache structure to cause the cache structure to prefetch information into the cache structure in anticipation of a demand request for that information being issued to the cache structure by the processor pipeline. The processor pipeline is arranged to issue a trigger to the prefetch circuitry on detection of a given event that will result in a reduced level of demand requests being issued by the processor pipeline, and the prefetch circuitry is configured to control issuing of prefetch requests in dependence on reception of the trigger.

公开(公告)号：US10725992B2

公开(公告)日：2020-07-28

申请号：US16207241

申请日：2018-12-03

申请人： ARM LIMITED

发明人： Mitchell Bryan Hayenga ,  Curtis Glenn Dunham ,  Dam Sunwoo

IPC分类号： G06F16/22 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1027 ,  G06F9/38 ,  G06F16/172 ,  G06F21/75

摘要： An apparatus has processing circuitry for processing instructions from multiple threads. A storage structure is shared between the threads and has a number of entries. Indexing circuitry generates a target index value identifying an entry of the storage structure to be accessed in response to a request from the processing circuitry specifying a requested index value corresponding to information to be accessed from the storage structure. The indexing circuitry generates the target index value as a function of the requested index value and a key value selected depending on which of the threads trigger the request. The key value for at least one of the threads is updated from time to time.

公开(公告)号：US11899583B2

公开(公告)日：2024-02-13

申请号：US17388927

申请日：2021-07-29

申请人： Arm Limited

发明人： Joshua Randall ,  Alejandro Rico Carro ,  Dam Sunwoo ,  Saurabh Pijuskumar Sinha ,  Jamshed Jalal

IPC分类号： G06F12/0811 ,  G06F12/084 ,  H04L45/42 ,  H04L49/109 ,  G06F12/0813 ,  G06F12/0893

CPC分类号： G06F12/0811 ,  G06F12/084 ,  G06F12/0813 ,  G06F12/0893 ,  H04L45/42 ,  H04L49/109

摘要： Various implementations described herein are directed to a device with a multi-layered logic structure with multiple layers including a first layer and a second layer arranged vertically in a stacked configuration. The device may have a first cache memory with first interconnect logic disposed in the first layer. The device may have a second cache memory with second interconnect logic disposed in the second layer, wherein the second interconnect logic in the second layer is linked to the first interconnect logic in the first layer.