摘要:
An Extremely High Frequency (EHF) dual-mode PA with a power combiner is designed using 40-nm bulk CMOS technology. One of the unit PAs can be switched off for the low power applications. In the design, circuit level optimization and trade-off are performed to ensure the good performance in both modes. The PA achieves a PSAT of 17.4 dBm with 29.3% PAE in high power mode and a PSAT of 12.6 dBm with 19.6% PAE in low power mode. The reliability measurements are also conducted and a lifetime of 80613 hours is estimated based on a commonly used empirical model. The excellent performance (e.g., highest reported PAE) achieved in this design further confirms the scaling of CMOS technology will continue to benefit the mm-wave transceiver design.
摘要:
A power amplifier configured to boost an AC signal. The power amplifier includes a first transistor, a second transistor, a first inductor connected between the first transistor and a voltage source, and a second inductor connected between the second transistor and ground. A first phase conditioner arranged at an input of the first transistor is configured to condition a phase of the AC signal such that the AC signal as received by the first transistor is out of phase with respect to the AC signal as received by the first inductor. A second phase conditioner arranged at an input of the second transistor is configured to condition a phase of the AC signal such that the AC signal as received by the second transistor is out of phase with respect to the AC signal as received by the second inductor.
摘要:
Apparatus and methods disclosed herein operate to receive a differential input signal at a first-stage pair of transconductance devices. The differential signal is amplified by a second-order factor at a positive-side or a negative-side first-stage transconductance device, depending upon the polarity of the differential input signal, to create a second-order signal at the output of the appropriate first-stage device. The second-order output signal is then amplified by another second-order factor at a corresponding second-stage transconductance device. A resulting fourth-order signal is made available at an output node as a quartic-response current source. The quartic-response current source may be utilized as a dynamic bias source in conjunction with a linear amplifier to provide a high slew rate amplifier.
摘要:
An operation amplifier (op-amp) and a circuit for providing dynamic current thereof are disclosed. The circuit can be applied to any current op-amp. The circuit comprises two transistors which are simultaneously or non-simultaneously turned on as the input signals respectively received by the first input and the second input of the op-amp get a transition, namely, as the op-amp is in the transient state, so as to increase the bias current at the first input terminal or/and the second input terminal of the op-amp by a dynamic current. Therefore, not only the internal slew rate of the op-amp can be accelerated by the circuit of the present invention, but also the power consumption of the op-amp can not be increased by the circuit of the present invention as the op-amp in the steady state.
摘要:
A transmission circuit includes a first-stage circuit, a second-stage circuit, a negative active feedback circuit and a current buffer. The first-stage circuit includes at least an active MOS device for receiving an input voltage and issuing a first voltage signal. The active MOS device has an inductive feature during operation in a high frequency mode to compensate the first voltage signal. In response to the first voltage signal, the second-stage circuit outputs a first output voltage. The negative active feedback circuit may enhance the bandwidth of the first output voltage. The current buffer may enhance the gain value of the first output voltage. A second voltage signal is issued from the first-stage circuit and compensated by the first output voltage transmitted from the current buffer to enhance the bandwidth and the gain value thereof. In response to the compensated second voltage signal, the second-stage circuit outputs a second output voltage.
摘要:
A circuit arrangement that stacks a modulator and automatic gain control (AGC) amplifier so as to re-use the modulator output current to drive the AGC amplifier, thereby saving power consumption and avoiding an unnecessary signal transformation between the two stages. A balanced circuit topology is used. The modulation signal can be selected over a wide range (100 MHz to 5.4 GHz) and the circuit arrangement is therefore particularly suitable for wireless applications (e.g. GSM-EDGE) and for integrated circuit fabrication.
摘要:
A translinear amplifier is disclosed. A loop amplifier drives the bases of the input and output transistor pairs from the differential collector voltage of the input pair. The loop amplifier contains a third differential pair (a gain pair). The tail current of the gain pair is inversely related to the tail current of the input pair, such that loop amplifier gain remains stable when the transconductance of the input pair changes (due, e.g., to input gain changes). In one embodiment, a linear-in-dB interface is provided that adjusts input pair tail current exponentially (and gain pair tail current exponentially and inversely) to linear voltage changes at a gain input.
摘要:
An electronic amplifier providing very low distortion which includes an output stage with an output error correction stage containing two amplifiers and wherein there are at least four local negative feedback paths, an output of the first amplifier being connected to an input of output stage transistor buffers or output stage transistors through a first network, an output of the second amplifier being connected to an input of output stage transistor buffers or output stage transistors through a second network, where components of the first and second amplifier the local negative feedback paths, first and second networks and output stage transistor buffers are selected to form substantially second order local dominant pole. Also disclosed is the supply of power to said first and second amplifiers from a floating power supply means coupled to either an or the output of the output stage so that the voltage of the floating power supply will follow substantially an output voltage of the output stage.
摘要:
A voltage subtractor/adder circuit comprises a differential pair having first and second MOS transistors. Gate electrodes of the first and second MOS transistors form input terminals for receiving an input differential voltage. Drain electrodes of the first and second MOS transistors form output terminals for outputting a subtraction output signal. Source electrodes of the first and second MOS transistors are commonly coupled to form an output terminal for addition output voltage. The sum of currents flowing through the first and second MOS transistors increases in proportion to the square of the input differential voltage. It is also possible to drive the differential pair by a constant current source. A level shifter may be provided for level-shifting the addition output voltage from the commonly coupled source electrodes.
摘要:
A circuit arrangement that stacks a modulator and automatic gain control (AGC) amplifier so as to re-use the modulator output current to drive the AGC amplifier, thereby saving power consumption and avoiding an unnecessary signal transformation between the two stages. A balanced circuit topology is used. The modulation signal can be selected over a wide range (100 MHz to 5.4 GHz) and the circuit arrangement is therefore particularly suitable for wireless applications (e.g. GSM-EDGE) and for integrated circuit fabrication.