公开(公告)号：US20090219092A1

公开(公告)日：2009-09-03

申请号：US12129364

申请日：2008-05-29

申请人： Jongsik KIM ,  Sangwon Han ,  Hyunchol Shin

发明人： Jongsik KIM ,  Sangwon Han ,  Hyunchol Shin

IPC分类号： H03F3/45 ,  H03G3/12

CPC分类号： H03F3/45188 ,  H03F1/223 ,  H03F1/3205 ,  H03F1/3211 ,  H03F3/195 ,  H03F3/45201 ,  H03F3/45677 ,  H03F3/4569 ,  H03F2200/108 ,  H03F2200/451 ,  H03F2203/45008 ,  H03F2203/45362 ,  H03F2203/45392 ,  H03F2203/45464 ,  H03F2203/45496

摘要： There is provided a highly linear differential amplifying circuit. The highly linear differential amplifying circuit includes: a differential amplifying unit including a main differential amplifying unit having a differential pair of transistors for amplifying a difference of two input signals and an auxiliary amplifying unit connected in parallel with the main differential amplifying unit, wherein second-order derivatives of transconductances of the main differential amplifying unit and the auxiliary differential amplifying unit are properly set to have an offset; and a source degeneration resistor unit including a first source degeneration resistor to a fourth source degeneration resistor. Accordingly, the linearity of the differential amplifying circuit is improved at a wide output power region.

摘要翻译： 提供了高度线性的差分放大电路。 高线性差分放大电路包括：差分放大单元，包括具有用于放大两个输入信号的差的晶体管的差分对的主差分放大单元和与主差分放大单元并联连接的辅助放大单元， 主差分放大单元和辅助差分放大单元的跨导的顺序导数被适当地设置为具有偏移; 以及源极退化电阻器单元，其包括到第四源极退变电阻器的第一源极退变电阻器。 因此，在宽的输出功率区域，差分放大电路的线性度得到改善。

公开(公告)号：US20070069817A1

公开(公告)日：2007-03-29

申请号：US11559195

申请日：2006-11-13

申请人： Mario Caresosa ,  Guangming Yin

发明人： Mario Caresosa ,  Guangming Yin

IPC分类号： H03G3/10

CPC分类号： H03F3/4569 ,  H03F3/45197 ,  H03F3/45744 ,  H03F2200/78 ,  H03F2203/45074 ,  H03F2203/45086 ,  H03F2203/45482 ,  H03F2203/45486 ,  H03G1/0088 ,  H03G3/3036 ,  H03G3/3052

摘要： A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain mode and the mode in which the VGA is currently operating in is adaptively sensed. A threshold voltage is compared to a control voltage of the VGA; if the VGA is currently operating in the low gain mode and the control voltage is higher than the threshold voltage, the VGA is switched from the low gain mode to the high gain mode; and if the VGA is currently operating in the high gain mode and the control voltage is lower than the threshold voltage, the VGA is switched from the high gain mode to the low gain mode.

摘要翻译： 一种用于自适应地控制可变增益放大器（VGA）的方法和装置。 VGA的操作被分为低增益模式和高增益模式，并且自适应地感测VGA当前正在操作的模式。 将门限电压与VGA的控制电压进行比较; 如果VGA当前处于低增益模式并且控制电压高于阈值电压，则VGA从低增益模式切换到高增益模式; 如果VGA当前处于高增益模式并且控制电压低于阈值电压，则VGA从高增益模式切换到低增益模式。

公开(公告)号：US20020060598A1

公开(公告)日：2002-05-23

申请号：US09940472

申请日：2001-08-29

申请人： NEC CORPORATION

发明人： Katsuji Kimura

IPC分类号： G06G007/14

CPC分类号： H03F3/45717 ,  G06G7/14 ,  H03F3/45183 ,  H03F3/4565 ,  H03F3/4569 ,  H03F3/45708 ,  H03F3/45739 ,  H03F2203/45456 ,  H03F2203/45484 ,  H03F2203/45566 ,  H03F2203/45612 ,  H03F2203/45702

摘要： A voltage subtractor/adder circuit comprises a differential pair having first and second MOS transistors. Gate electrodes of the first and second MOS transistors form input terminals for receiving an input differential voltage. Drain electrodes of the first and second MOS transistors form output terminals for outputting a subtraction output signal. Source electrodes of the first and second MOS transistors are commonly coupled to form an output terminal for addition output voltage. The sum of currents flowing through the first and second MOS transistors increases in proportion to the square of the input differential voltage. It is also possible to drive the differential pair by a constant current source. A level shifter may be provided for level-shifting the addition output voltage from the commonly coupled source electrodes.

摘要翻译： 电压减法器/加法器电路包括具有第一和第二MOS晶体管的差分对。 第一和第二MOS晶体管的栅电极形成用于接收输入差分电压的输入端。 第一和第二MOS晶体管的漏极形成用于输出减法输出信号的输出端。 第一和第二MOS晶体管的源电极共同耦合以形成用于加法输出电压的输出端。 流过第一和第二MOS晶体管的电流的总和与输入差分电压的平方成比例地增加。 也可以通过恒定电流源来驱动差分对。 可以提供电平移位器用于对来自共同耦合的源电极的相加输出电压进行电平移位。

公开(公告)号：US07030697B1

公开(公告)日：2006-04-18

申请号：US10717344

申请日：2003-11-18

申请人： Maxim Pribytko ,  Patrick J. Quinn

发明人： Maxim Pribytko ,  Patrick J. Quinn

IPC分类号： H03F3/45

CPC分类号： H03F3/4569 ,  H03F3/45192 ,  H03F2203/45028

摘要： A method and apparatus for providing high common-mode rejection ratio (CMRR) in a single-ended CMOS operational transconductance amplifier is disclosed. A common-mode feedback boosts the OTA CMRR, while allowing integration of conventional OTA improvements.

摘要翻译： 公开了一种在单端CMOS运算跨导放大器中提供高共模抑制比（CMRR）的方法和装置。 共模反馈增强了OTA CMRR，同时允许集成传统的OTA改进。

公开(公告)号：US20030052731A1

公开(公告)日：2003-03-20

申请号：US10234129

申请日：2002-09-05

申请人： NEC CORPORATION

发明人： Katsuji Kimura

IPC分类号： G06G007/12

CPC分类号： H03F3/45717 ,  G06G7/14 ,  H03F3/45183 ,  H03F3/4565 ,  H03F3/4569 ,  H03F3/45708 ,  H03F3/45739 ,  H03F2203/45456 ,  H03F2203/45484 ,  H03F2203/45566 ,  H03F2203/45612 ,  H03F2203/45702

摘要： A voltage subtractor/adder circuit comprises a differential pair having first and second MOS transistors. Gate electrodes of the first and second MOS transistors form input terminals for receiving an input differential voltage. Drain electrodes of the first and second MOS transistors form output terminals for outputting a subtraction output signal. Source electrodes of the first and second MOS transistors are commonly coupled to form an output terminal for addition output voltage. The sum of currents flowing through the first and second MOS transistors increases in proportion to the square of the input differential voltage. It is also possible to drive the differential pair by a constant current source. A level shifter may be provided for level-shifting the addition output voltage from the commonly coupled source electrodes.

公开(公告)号：US5283535A

公开(公告)日：1994-02-01

申请号：US937313

申请日：1992-09-01

申请人： Joannes M. J. Sevenhans ,  Mark G. S. J. Van Paemel

发明人： Joannes M. J. Sevenhans ,  Mark G. S. J. Van Paemel

IPC分类号： H03F1/32 ,  H03F3/45

CPC分类号： H03F3/45179 ,  H03F1/3211 ,  H03F3/45183 ,  H03F3/4569 ,  H03F3/45739 ,  H03F2203/45008 ,  H03F2203/45074 ,  H03F2203/45078 ,  H03F2203/45466 ,  H03F2203/45612 ,  H03F2203/45641 ,  H03F2203/45648

摘要： An arrangement includes a differential amplifier pair configured as first and second amplifier branches with first and second input terminals respectively. The first and second amplifier branches are connected at a junction point to a common branch which includes a current source. A control circuit regulates the current of the current source to linearize an input/output characteristic of the amplifier differential pair. The control circuit includes a negative feedback circuit having a comparator, a first input of the comparator being connected to a reference voltage terminal to which an external reference voltage is applied, a second input of the comparator being connected to the amplifier branch junction point and an output of the comparator connected for controlling the current source.

摘要翻译： 一种布置包括分别配置有第一和第二输入端的第一和第二放大器的差分放大器对。 第一和第二放大器分支在连接点处连接到包括电流源的公共分支。 控制电路调节电流源的电流以使放大器差分对的输入/输出特性线性化。 所述控制电路包括具有比较器的负反馈电路，所述比较器的第一输入端连接到施加了外部参考电压的基准电压端子，所述比较器的第二输入端连接到所述放大器支路连接点， 用于控制电流源的比较器的输出。

公开(公告)号：US20180173670A1

公开(公告)日：2018-06-21

申请号：US15847555

申请日：2017-12-19

申请人： HUAWEI TECHNOLOGIES CO., LTD.

发明人： Junming HAN ,  Bingzhao ZHANG ,  Jie PENG ,  Yongwang LIU

IPC分类号： G06F13/42 ,  H03F3/45 ,  G06F13/40

CPC分类号： G06F13/4282 ,  G06F13/4072 ,  H03F3/2171 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/45659 ,  H03F3/4569 ,  H03F2203/45276 ,  H03F2203/45418 ,  H03F2203/45426 ,  H03F2203/45466

摘要： A drive circuit for a serial communications system is provided. The drive circuit may include a mode controller, a pre-drive circuit, and a main drive circuit. The main drive circuit includes multiple mode control switches and at least one pair of differential switches. The mode controller is configured to: generate a mode control signal, and transmit the mode control signal to the main drive circuit. The pre-drive circuit is configured to: convert a differential digital signal into a differential control signal, and transmit the differential control signal to the main drive circuit. The main drive circuit controls on/off states of the multiple mode control switches according to the mode control signal, and works in corresponding working modes. The drive circuit controls the states of the mode control switches in the main drive circuit, so that the main drive circuit works in different working modes.

公开(公告)号：US07696791B2

公开(公告)日：2010-04-13

申请号：US11968143

申请日：2007-12-31

申请人： Sami Hyvonen

发明人： Sami Hyvonen

IPC分类号： H03K5/22

CPC分类号： H03F3/45183 ,  H03F3/19 ,  H03F3/45188 ,  H03F3/4569 ,  H03F2200/451 ,  H03F2203/45424 ,  H03F2203/45466 ,  H03F2203/45596 ,  H03F2203/45691 ,  H03F2203/45701 ,  H03K5/1532

摘要： An amplitude detection circuit using a sinusoidal input signal inputs to produce a digital output (a one or zero) is described. The circuit uses an input field effect transistor (FET) with a gate load coupled to a gate of the input FET. A drain load may be coupled to a drain of the input FET. A source load may be coupled to a source of the input FET. A controllable variable current generator provides a current to the source of the input FET, biasing the source of the input FET to a reference voltage. An input signal conductor may be coupled to the gate of the input FET. Other embodiments are described.

摘要翻译： 描述使用正弦输入信号输入以产生数字输出（一个或零）的振幅检测电路。 该电路使用具有耦合到输入FET的栅极的栅极负载的输入场效应晶体管（FET）。 漏极负载可以耦合到输入FET的漏极。 源负载可以耦合到输入FET的源极。 可控可变电流发生器向输入FET的源极提供电流，将输入FET的源极偏置为参考电压。 输入信号导体可以耦合到输入FET的栅极。 描述其他实施例。

公开(公告)号：US06657486B2

公开(公告)日：2003-12-02

申请号：US10234129

申请日：2002-09-05

申请人： Katsuji Kimura

发明人： Katsuji Kimura

IPC分类号： G06G726

CPC分类号： H03F3/45717 ,  G06G7/14 ,  H03F3/45183 ,  H03F3/4565 ,  H03F3/4569 ,  H03F3/45708 ,  H03F3/45739 ,  H03F2203/45456 ,  H03F2203/45484 ,  H03F2203/45566 ,  H03F2203/45612 ,  H03F2203/45702

摘要： A MOS differential amplifier circuit has a differential pair having first and second MOS transistors. The source electrodes of the first and second MOS transistors are commonly coupled and driven by a current source, which can be adjusted to change the transconductance of the amplifier. The circuit can be provided with a quadri-tall cell or level shifter in order to provide this operation. With these operational characteristics, the MOS differential pair of this type can be used in a voltage adder/subtractor circuit.

摘要翻译： MOS差分放大器电路具有具有第一和第二MOS晶体管的差分对。 第一和第二MOS晶体管的源极通常由电流源耦合和驱动，电流源可以被调节以改变放大器的跨导。 为了提供这种操作，该电路可以设置有四节细胞或电平移位器。 利用这些操作特性，这种类型的MOS差分对可以用在电压加法器/减法器电路中。

公开(公告)号：US06657485B2

公开(公告)日：2003-12-02

申请号：US10137298

申请日：2002-05-03

申请人： Katsuji Kimura

发明人： Katsuji Kimura

IPC分类号： G06G712

CPC分类号： H03F3/45717 ,  G06G7/14 ,  H03F3/45183 ,  H03F3/4565 ,  H03F3/4569 ,  H03F3/45708 ,  H03F3/45739 ,  H03F2203/45456 ,  H03F2203/45484 ,  H03F2203/45566 ,  H03F2203/45612 ,  H03F2203/45702

摘要： A MOS differential amplifier circuit has a differential pair having first and second MOS transistors. The source electrodes of the first and second MOS transistors are commonly coupled and driven by a constant current source. The current sources can be controlled so that the difference between the common mode voltage and the common source voltage becomes constant, and a level shifter may be provided for level-shifting the common source voltage of the first and second MOS transistor. The MOS differential amplifier circuit so designed can be used in a voltage adder/subtractor circuit.

摘要翻译： MOS差分放大器电路具有具有第一和第二MOS晶体管的差分对。 第一和第二MOS晶体管的源电极通常由恒定电流源耦合和驱动。 可以控制电流源，使得共模电压和公共源电压之间的差变为恒定，并且可以提供电平移位器来对第一和第二MOS晶体管的公共源电压进行电平移位。 这样设计的MOS差分放大器电路可以用在电压加法器/减法器电路中。