公开(公告)号：US09870834B2

公开(公告)日：2018-01-16

申请号：US15298171

申请日：2016-10-19

Applicant: California Institute of Technology

Inventor： Yue Li ,  Jehoshua Bruck

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/16 ,  G11C16/10 ,  G11C16/04 ,  G11C29/44 ,  G11C29/04

CPC classification number: G11C16/3495 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/16 ,  G11C29/44 ,  G11C2029/0409 ,  G11C2211/5641

Abstract: A data device includes a memory having a plurality of memory cells configured to store data values in accordance with a predetermined rank modulation scheme that is optional and a memory controller that receives a current error count from an error decoder of the data device for one or more data operations of the flash memory device and selects an operating mode for data scrubbing in accordance with the received error count and a program cycles count.

公开(公告)号：US20180012663A1

公开(公告)日：2018-01-11

申请号：US15639052

申请日：2017-06-30

Applicant: Seagate Technology LLC

Inventor： AbdelHakim S. Alhussien ,  Sundararajan Sankaranarayanan ,  Erich F. Haratsch

IPC: G11C16/26 ,  G06F11/10 ,  G11C29/52 ,  H03M13/11

CPC classification number: G11C16/26 ,  G06F11/1012 ,  G06F11/1068 ,  G11C11/5642 ,  G11C16/28 ,  G11C29/021 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411 ,  H03M13/1105 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/3707 ,  H03M13/3723 ,  H03M13/612 ,  H03M13/6325

Abstract: Independent read threshold voltage tracking techniques are provided for multiple dependent read threshold voltages using syndrome weights. An exemplary method comprises reading codewords of a plurality of pages using different first read threshold voltages and a default second read threshold voltage; applying read values for the plurality of pages for the different first read threshold voltages and the default second read threshold voltage to a decoder; aggregating a syndrome weight for each failed decoding attempt for the different first read threshold voltages; identifying a reading having a substantially minimum syndrome weight as a substantially optimum first read threshold voltage; reading codewords of the plurality of pages using the substantially optimum first read threshold voltage and different second read threshold voltages; applying read values for the substantially optimum first read threshold voltage and the different second read threshold voltages to the decoder; aggregating the syndrome weight for the different second read threshold voltages; and identifying a reading having a substantially minimum syndrome weight as a substantially optimum second read threshold voltage.

公开(公告)号：US20180004592A1

公开(公告)日：2018-01-04

申请号：US15650479

申请日：2017-07-14

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  George VERGIS

IPC: G06F11/10 ,  G11C29/44 ,  G11C7/10 ,  G11C29/42 ,  G11C5/04 ,  G11C29/04

CPC classification number: G06F11/10 ,  G06F11/108 ,  G11C5/04 ,  G11C7/1063 ,  G11C29/42 ,  G11C29/44 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A memory subsystem has multiple memory devices coupled to a command/address line and an error alert line, the error alert line delay-compensated to provide deterministic alert signal timing. The command/address line and the error alert line are connected between the memory devices and a memory controller that manages the memory devices. The command/address line is driven by the memory controller, and the error alert line is driven by the memory devices.

公开(公告)号：US20170372798A1

公开(公告)日：2017-12-28

申请号：US15699833

申请日：2017-09-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Katsuhiko HOYA

IPC: G11C29/42 ,  G11C29/52 ,  G06F11/10

CPC classification number: G11C29/42 ,  G06F11/106 ,  G11C11/1677 ,  G11C16/349 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A memory device of one embodiment includes memory elements which store data and parity; a first decoder which, when scrubbing of the data is performed while no external access is being made to the memory device, uses a syndrome generated from the data and the parity to correct an error of a maximum of N bits in a unit of the data; and a second decoder which, when reading of the data is performed, uses the syndrome to correct an error of a maximum of M bits in a unit of the data. The N bits represent the number of bits smaller than the N bits.

公开(公告)号：US09846614B1

公开(公告)日：2017-12-19

申请号：US15173091

申请日：2016-06-03

Applicant: International Business Machines Corporation

Inventor： Brian D. Barrick ,  James W. Bishop ,  Maarten J. Boersma ,  Marcy E. Byers ,  Sundeep Chadha ,  Jentje Leenstra ,  Dung Q. Nguyen ,  David R. Terry

IPC: G06F11/10 ,  G11C29/52 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F11/106 ,  G06F9/30098 ,  G06F9/3016 ,  G06F9/3855 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: Techniques for error correction in a processor include detecting an error in first data stored in a register. The method also includes generating an instruction to read the first data stored in the register, where the register is both a source register and a destination register of the instruction. The method further includes transmitting the first data and error correcting code data to an execution unit, where the first data and error correcting code data bypasses an issue queue. The method also includes decoding the instruction and correcting the error to generate corrected data and writing the corrected data to the destination register.

公开(公告)号：US20170351308A1

公开(公告)日：2017-12-07

申请号：US15674594

申请日：2017-08-11

Applicant: Intel Corporation

Inventor： Thanunathan Rangarajan ,  Vinayak P. Risbud ,  Tabassum Yasmin

IPC: G06F1/20 ,  G11C7/04 ,  G11C29/00 ,  G11C29/46 ,  G11C29/20 ,  G11C29/04 ,  G11C5/04

CPC classification number: G06F1/206 ,  G06F11/3037 ,  G06F11/3058 ,  G11C5/04 ,  G11C7/04 ,  G11C29/20 ,  G11C29/46 ,  G11C29/52 ,  G11C29/76 ,  G11C2029/0407 ,  G11C2029/0409 ,  Y02D10/16

Abstract: In an embodiment, a processor includes at least one core to execute instructions and a memory controller coupled to the at least one core. In turn, the memory controller includes a spare logic to cause a dynamic transfer of data stored on a first memory device coupled to the processor to a second memory device coupled to the processor, responsive to a temperature of the first memory device exceeding a thermal threshold. Other embodiments are described and claimed.

公开(公告)号：US20170345489A1

公开(公告)日：2017-11-30

申请号：US15215913

申请日：2016-07-21

Applicant: Lite-On Electronics (Guangzhou) Limited ,  Lite-On Technology Corporation

Inventor： Shih-Jia Zeng ,  Jen-Chien Fu

IPC: G11C11/56 ,  G11C16/26 ,  G06F11/10 ,  G11C16/04 ,  G06F3/06 ,  G11C29/52 ,  G11C16/10

CPC classification number: G11C11/5642 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1048 ,  G06F11/1068 ,  G11C11/5628 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A solid state storage includes a non-volatile memory and a controlling circuit. The non-volatile memory includes a first block. The controlling circuit is connected with the non-volatile memory. The controlling circuit includes a function storage circuit. The function storage circuit stores plural prediction functions. According to plural state parameters corresponding to the first block and a first prediction function of the plural prediction functions, the controlling circuit predicts a read voltage shift of the first block.

公开(公告)号：US09830219B2

公开(公告)日：2017-11-28

申请号：US14627580

申请日：2015-02-20

Applicant: Western Digital Technologies, Inc.

Inventor： Robert Mateescu ,  Yongjune Kim ,  Zvonimir Z. Bandic ,  Seung-Hwan Song

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52 ,  G11C11/56 ,  G11C29/44 ,  G11C16/00 ,  G11C29/04

CPC classification number: G06F11/1068 ,  G06F11/1072 ,  G11C11/5628 ,  G11C16/00 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0409

Abstract: Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including writing first data to the memory, reading the first data from the memory, analyzing the first read data such that the analyzing includes determining whether the read data includes an error, encoding second data based on the analyzing of the first data such that the second data is encoded to be written to a position adjacent to the error when it is determined that the read data includes the error, and writing the encoded second data to the memory at the position.

公开(公告)号：US09830098B1

公开(公告)日：2017-11-28

申请号：US15207456

申请日：2016-07-11

Applicant: Silicon Motion, Inc.

Inventor： Sheng-Liu Lin

IPC: G11C16/04 ,  G06F3/06 ,  G11C16/10

CPC classification number: G06F3/0659 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0679 ,  G11C16/10 ,  G11C16/349 ,  G11C16/3495 ,  G11C29/52 ,  G11C29/70 ,  G11C2029/0409

Abstract: A method of wear leveling for a data storage device is provided. The data storage device includes a non-volatile memory having a plurality of blocks. A portion of the blocks not having any valid data are defined as spare blocks, and the spare blocks are associated with a spare pool. The method includes the steps of: maintaining a management table recording a plurality of physical block numbers and a plurality of block statuses corresponding to the blocks; selecting a first spare block having a first smallest physical block number as a current temporary block; receiving a write command from a host; determining whether data in the write command shall be written into the current temporary block; if false, selecting a second spare block having a second smallest physical block number as a next temporary block; and writing the data into the next temporary block.

公开(公告)号：US09817384B2

公开(公告)日：2017-11-14

申请号：US14660106

申请日：2015-03-17

Applicant: JTEKT CORPORATION

Inventor： Kenichi Ikegami

IPC: G11C29/00 ,  G05B19/05 ,  G11C29/04

CPC classification number: G05B19/058 ,  G05B2219/14085 ,  G11C2029/0409

Abstract: A method of inspecting a RAM of a programmable logic controller is provided that enables all unit storage regions in a RAM inspection region to be inspected in about several minutes and that meets a predetermined safety standard. The inspection method includes the steps of: (a) dividing a RAM inspection region, which is a region of the RAM to be inspected, into a plurality of blocks; and (b) by a control device, writing a predetermined value into unit storage regions in a combination of blocks obtained by combining two blocks extracted from the divided blocks and thereafter sequentially inspecting whether or not values read from the unit storage regions each coincide with the written value. Step (b) is executed for all combinations of two blocks extracted from the divided blocks.