公开(公告)号：US09601434B2

公开(公告)日：2017-03-21

申请号：US12964823

申请日：2010-12-10

Applicant: Yaojian Lin ,  Kang Chen ,  Jianmin Fang

Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang

IPC: H01L23/52 ,  H01L23/538 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/2101 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over a portion of the encapsulant within an interconnect site outside a footprint of the semiconductor die. An opening is formed through the first insulating layer within the interconnect site to expose the encapsulant. The opening can be ring-shaped or vias around the interconnect site and within a central region of the interconnect site to expose the encapsulant. A first conductive layer is formed over the first insulating layer to follow a contour of the first insulating layer. A second conductive layer is formed over the first conductive layer and exposed encapsulant. A second insulating layer is formed over the second conductive layer. A bump is formed over the second conductive layer in the interconnect site.

公开(公告)号：US09082832B2

公开(公告)日：2015-07-14

申请号：US13478008

申请日：2012-05-22

Applicant: Yaojian Lin ,  Kang Chen ,  Jianmin Fang

Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang

IPC: H01L21/50 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L21/76898 ,  H01L21/481 ,  H01L21/486 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0347 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/0554 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/48091 ,  H01L2224/73104 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01007 ,  H01L2924/01023 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.

Abstract translation: 半导体器件具有带有多个接触焊盘的半导体晶片。 在半导体晶片和接触焊盘上形成第一绝缘层。 去除第一绝缘层的一部分，暴露接触焊盘的第一部分，同时留下覆盖的接触焊盘的第二部分。 在接触焊盘和第一绝缘层之上形成凸起下金属化层和多个凸点。 在第一绝缘层，凸块下金属化层的侧壁，凸起的侧壁和凸块的上表面上形成第二绝缘层。 去除了覆盖凸起的上表面的第二绝缘层的一部分，但是第二绝缘层保持在突起的侧壁和凸块下金属化层的侧壁上。

公开(公告)号：US09082780B2

公开(公告)日：2015-07-14

申请号：US13428439

申请日：2012-03-23

Applicant: Yaojian Lin ,  Kang Chen ,  Yu Gu

Inventor： Yaojian Lin ,  Kang Chen ,  Yu Gu

IPC: H01L21/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H01L23/538

CPC classification number: H01L21/563 ,  H01L21/568 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/19 ,  H01L2924/00012 ,  H01L2224/03

Abstract: A semiconductor device has a semiconductor die. An encapsulant is deposited around the semiconductor die. An interconnect structure having a conductive bump is formed over the encapsulant and semiconductor die. A mechanical support layer is formed over the interconnect structure and around the conductive bump. The mechanical support layer is formed over a corner of the semiconductor die and over a corner of the interconnect structure. An opening is formed through the encapsulant that extends to the interconnect structure. A conductive material is deposited within the opening to form a conductive through encapsulant via (TEV) that is electrically connected to the interconnect structure. A semiconductor device is mounted to the TEV and over the semiconductor die to form a package-on-package (PoP) device. A warpage balance layer is formed over the encapsulant opposite the interconnect structure.

Abstract translation: 半导体器件具有半导体管芯。 围绕半导体管芯沉积密封剂。 具有导电凸块的互连结构形成在密封剂和半导体管芯上。 机械支撑层形成在互连结构上并且围绕导电凸块。 机械支撑层形成在半导体管芯的拐角上并且在互连结构的拐角上。 通过延伸到互连结构的密封剂形成开口。 导电材料沉积在开口内以形成导电的通过密封剂通过（TEV）电连接到互连结构。 将半导体器件安装到TEV并在半导体管芯上方形成封装封装（PoP）器件。 在与互连结构相对的密封剂上形成翘曲平衡层。

公开(公告)号：US08907476B2

公开(公告)日：2014-12-09

申请号：US13446664

申请日：2012-04-13

Applicant: Yaojian Lin ,  Kang Chen ,  Jianmin Fang ,  Xia Feng

Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang ,  Xia Feng

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/538 ,  H01L21/78 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L21/31051 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/49816 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/94 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2224/03

Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant.

Abstract translation: 半导体晶片包含由锯条分隔开的多个半导体管芯。 在半导体晶片上形成绝缘层。 在绝缘层上形成保护层，该保护层包括沿着锯条的半导体管芯的边缘。 保护层覆盖半导体晶片的整个表面。 或者，在锯路上的保护层中形成开口。 绝缘层具有非平面表面，保护层具有平坦表面。 通过保护层和锯条将半导体晶片分离，以分离半导体管芯，同时保护半导体管芯的边缘。 与保护层一起，将半导体管芯安装到载体上。 密封剂沉积在半导体管芯和载体上。 去除载体和保护层。 在半导体管芯和密封剂上形成积层互连结构。

公开(公告)号：US08610286B2

公开(公告)日：2013-12-17

申请号：US13315010

申请日：2011-12-08

Applicant: Yaojian Lin ,  Kang Chen ,  Jose Alvin Caparas ,  Glenn Omandam

Inventor： Yaojian Lin ,  Kang Chen ,  Jose Alvin Caparas ,  Glenn Omandam

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/315 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die mounted to a carrier. A first encapsulant is deposited over the semiconductor die and carrier. A stiffening support member can be disposed over the carrier around the semiconductor die. A plurality of channels or recesses is formed in the first encapsulant. The recesses can be formed by removing a portion of the first encapsulant. Alternatively, the recesses are formed in a chase mold having a plurality of extended surfaces. A second encapsulant can be deposited into the recesses of the first encapsulant. The carrier is removed and an interconnect structure is formed over the semiconductor die and first encapsulant. The thickness of the first encapsulant provides sufficient stiffness to reduce warpage while the recesses provide stress relief during formation of the interconnect structure. A portion of the first encapsulant and recesses are removed to reduce thickness of the semiconductor device.

Abstract translation: 半导体器件具有安装到载体上的半导体管芯。 第一密封剂沉积在半导体管芯和载体上。 加强支撑构件可以设置在半导体管芯周围的载体上。 在第一密封剂中形成多个通道或凹槽。 可以通过去除第一密封剂的一部分来形成凹陷。 或者，凹部形成在具有多个延伸表面的追逐模具中。 可以将第二密封剂沉积到第一密封剂的凹部中。 移除载体并且在半导体管芯和第一密封剂上形成互连结构。 第一密封剂的厚度提供足够的刚度以减少翘曲，同时凹槽在形成互连结构期间提供应力释放。 去除第一密封剂和凹部的一部分以减小半导体器件的厚度。

公开(公告)号：US20130147054A1

公开(公告)日：2013-06-13

申请号：US13315010

申请日：2011-12-08

Applicant: Yaojian Lin ,  Kang Chen ,  Jose Alvin Caparas ,  Glenn Omandam

Inventor： Yaojian Lin ,  Kang Chen ,  Jose Alvin Caparas ,  Glenn Omandam

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L23/315 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die mounted to a carrier. A first encapsulant is deposited over the semiconductor die and carrier. A stiffening support member can be disposed over the carrier around the semiconductor die. A plurality of channels or recesses is formed in the first encapsulant. The recesses can be formed by removing a portion of the first encapsulant. Alternatively, the recesses are formed in a chase mold having a plurality of extended surfaces. A second encapsulant can be deposited into the recesses of the first encapsulant. The carrier is removed and an interconnect structure is formed over the semiconductor die and first encapsulant. The thickness of the first encapsulant provides sufficient stiffness to reduce warpage while the recesses provide stress relief during formation of the interconnect structure. A portion of the first encapsulant and recesses are removed to reduce thickness of the semiconductor device.

Abstract translation: 半导体器件具有安装到载体上的半导体管芯。 第一密封剂沉积在半导体管芯和载体上。 加强支撑构件可以设置在半导体管芯周围的载体上。 在第一密封剂中形成多个通道或凹槽。 可以通过去除第一密封剂的一部分来形成凹部。 或者，凹部形成在具有多个延伸表面的追逐模具中。 可以将第二密封剂沉积到第一密封剂的凹部中。 移除载体并且在半导体管芯和第一密封剂上形成互连结构。 第一密封剂的厚度提供足够的刚度以减少翘曲，同时凹槽在形成互连结构期间提供应力释放。 去除第一密封剂和凹部的一部分以减小半导体器件的厚度。

公开(公告)号：US20130069227A1

公开(公告)日：2013-03-21

申请号：US13478008

申请日：2012-05-22

Applicant: Yaojian Lin ,  Kang Chen ,  Jianmin Fang

Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang

IPC: H01L23/485 ,  H01L21/78 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/481 ,  H01L21/486 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0347 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/0554 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/48091 ,  H01L2224/73104 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01007 ,  H01L2924/01023 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.

公开(公告)号：US20130069225A1

公开(公告)日：2013-03-21

申请号：US13239080

申请日：2011-09-21

Applicant: Yaojian Lin ,  Kang Chen ,  Jianmin Fang

Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang

IPC: H01L21/768 ,  H01L23/485 ,  H01L21/78

CPC classification number: H01L21/76898 ,  H01L21/481 ,  H01L21/486 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0347 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/0554 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/48091 ,  H01L2224/73104 ,  H01L2224/73265 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01007 ,  H01L2924/01023 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.

Abstract translation: 半导体器件具有带有多个接触焊盘的半导体晶片。 在半导体晶片和接触焊盘上形成第一绝缘层。 去除第一绝缘层的一部分，暴露接触焊盘的第一部分，同时留下覆盖的接触焊盘的第二部分。 在接触焊盘和第一绝缘层之上形成凸起下金属化层和多个凸点。 在第一绝缘层，凸块下金属化层的侧壁，凸起的侧壁和凸块的上表面上形成第二绝缘层。 去除了覆盖凸起的上表面的第二绝缘层的一部分，但是第二绝缘层保持在凸块的侧壁和凸块下金属化层的侧壁上。

公开(公告)号：US20130015554A1

公开(公告)日：2013-01-17

申请号：US13615308

申请日：2012-09-13

Applicant: Yaojian Lin ,  Haijing Cao ,  Qing Zhang ,  Kang Chen ,  Jianmin Fang

Inventor： Yaojian Lin ,  Haijing Cao ,  Qing Zhang ,  Kang Chen ,  Jianmin Fang

IPC: H01L29/86 ,  H01L21/02

CPC classification number: H01L25/16 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L25/0652 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/2518 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2224/05599

Abstract: A semiconductor wafer contains a substrate having a plurality of active devices formed thereon. An analog circuit is formed on the substrate. The analog circuit can be an inductor, metal-insulator-metal capacitor, or resistor. The inductor is made with copper. A through substrate via (TSV) is formed in the substrate. A conductive material is deposited in the TSV in electrical contact with the analog circuit. An under bump metallization layer is formed on a backside of the substrate in electrical contact with the TSV. A solder material is deposited on the UBM layer. The solder material is reflowed to form a solder bump. A wire bond is formed on a top surface of the substrate. A redistribution layer is formed between the TSV and UBM. The analog circuit electrically connects through the TSV to the solder bump on the back side of the substrate.

Abstract translation: 半导体晶片包含其上形成有多个有源器件的衬底。 在基板上形成模拟电路。 模拟电路可以是电感，金属 - 绝缘体 - 金属电容或电阻。 电感由铜制成。 在衬底中形成贯穿衬底通孔（TSV）。 导电材料沉积在与模拟电路电接触的TSV中。 在与TSV电接触的衬底的背面上形成凸起下金属化层。 焊料材料沉积在UBM层上。 焊料材料被回流以形成焊料凸块。 在基板的顶表面上形成引线接合。 在TSV和UBM之间形成再分配层。 模拟电路通过TSV电连接到衬底背面的焊料凸块。

公开(公告)号：US08263437B2

公开(公告)日：2012-09-11

申请号：US12205755

申请日：2008-09-05

Applicant: Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

Inventor： Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

IPC: H01L21/00

CPC classification number: H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L25/03 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81805 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device has a first conductive layer formed over a sacrificial substrate. A first integrated passive device (IPD) is formed in a first region over the first conductive layer. A conductive pillar is formed over the first conductive layer. A high-resistivity encapsulant greater than 1.0 kohm-cm is formed over the first IPD to a top surface of the conductive pillar. A second IPD is formed over the encapsulant. The first encapsulant has a thickness of at least 50 micrometers to vertically separate the first and second IPDs. An insulating layer is formed over the second IPD. The sacrificial substrate is removed and a second semiconductor die is disposed on the first conductive layer. A first semiconductor die is formed in a second region over the substrate. A second encapsulant is formed over the second semiconductor die and a thermally conductive layer is formed over the second encapsulant.

Abstract translation: 半导体器件具有形成在牺牲衬底上的第一导电层。 第一集成无源器件（IPD）形成在第一导电层上的第一区域中。 在第一导电层上形成导电柱。 在第一IPD上形成大于1.0kohm-cm的高电阻率密封剂到导电柱的顶表面。 在密封剂上形成第二个IPD。 第一密封剂具有至少50微米的厚度以垂直分离第一和第二IPD。 绝缘层形成在第二IPD上。 去除牺牲基板，在第一导电层上设置第二半导体管芯。 第一半导体管芯形成在衬底上的第二区域中。 在第二半导体管芯上形成第二密封剂，并且在第二密封剂上形成导热层。